TMC4331A Datasheet | Document Revision 1.00 • 2016-NOV-10
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Pin Names and Descriptions
Number Type Function
Interface Pins for Stepper Motor Drivers
Pin
NSCSDRV
PWMB
Low active chip selects output of SPI interface to motor driver.
Second PWM signal (Cosine) to connect with PHB (TMC23x/24x).
O
O
24
23
21
SCKDRV
MDBN
Serial clock output of SPI interface to motor driver.
MDBN output signal for MDBN pin of TMC23x/24x.
SDODRV
PWMA
Serial data output of SPI interface to motor driver.
First PWM signal (Sine) to connect with PHA (TMC23x/24x).
IO
SDIDRV
ERR
Serial data input of SPI interface to motor driver.
Error input signal to ERR pin of TMC23x/24x.
If not connected, internal pull-down resistor is active.
I (PD)
I (PD)
22
7
DC_IN as external dcStep input control signal.
If not connected, internal pull-down resistor is active.
MP1
DCSTEP_ENABLE as dcStep output control signal.
SPE_OUT as output signal, connect to SPE pin of TMC23x/24x.
IO
O
MP2
8
STDBY_CLK
26
StandBy signal or internal CLK output or ChopSync output.
Table 2: Pin Names and Descriptions
System Overview
VDD1V8(2x)
CLK_EXT
I
GND(4x)
VDD5(3x)
Host CPU
SPI Interface
RES
POR
O
O
TARGET_REACHED
INTR
I
I
NSCSIN
SCKIN
SDIIN
Status flags +
Events à
Interrupt
Control
SPI
Register Block
I
O
SDOIN
Target
Register(s)
Parameters
from/for all
Units
Start / Stop /
Reference Switches
Timer Unit
PulseGen
v
or
or
IO
Step/Dir Output
PWM Output
DAC Output
START
O
O
STPOUT
PWMA
(Sine)
DACA
(Sine)
Internal
Step
Ramp
Status
DIROUT
PWMB
DACB
(Cosine)
(Cosine)
I
I
I
STOPL
HOME_REF
STOPR
Pos
Counter
Internal
Pos
Reference
processing
Ramp-Generator
S-ramps with 4 bows,
trapezoid, rectangle, ...
FS
Internal
(Co)Sine
LUT
Actual
Co-/Sine
values
Scale Unit
StdBy
signal
or
NSTDBY_OUT
Clk-Out
ChopSync Clk
CoverReg
Scaled
current
values
O
ChopSync
Unit
or
Drv type
PWM
Unit
PWM or DAC
encrypted co-/sine
voltage values
SPI Datagram Generator
I
Scan Test
TEST_MODE
DAC
Unit
I
IO
O
O
SDIDRV
SCKDRV
SPI Output
NSCSDRV
SDODRV
Figure 7: System Overview
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