TMC5072 DATASHEET (Rev. 1.22 / 2017-MAY-16)
10
Pin
Number Type
Function
5V supply input for digital circuitry within chip and charge pump.
Attach 470nF capacitor to GND (GND plane). May be supplied by
5VOUT. A 2.2Ω resistor is recommended for decoupling noise from
5VOUT. When using an external supply, make sure, that VCC comes
up before or in parallel to 5VOUT or VCC_IO, whichever comes up
later!
VCC
33
Connect the exposed die pad to a GND plane. Provide as many as
possible vias for heat transfer to GND plane.
DIE_PAD
-
GND
Table 2.1 Low voltage digital and analog power supply pins
Pin
Number Type
Function
Charge pump driver output. Outputs 5V (GND to VCC) square wave
with 1/16 of internal oscillator frequency.
Charge pump capacitor input: Provide external 22nF or 33nF / 50V
capacitor to CPO.
CPO
35
36
37
O(VCC)
CPI
I(VCP)
Output of charge pump. Provide external 100nF capacitor to VS.
VCP
Table 2.2 Charge pump pins
Pin
Number Type
Function
Input A for incremental encoder 1. Can be programmed to provide
positive active interrupt output based on ramp generator flags
RAMP_STAT bits 4, 5, 6 & 7 and encoder null event status
ENC_STATUS bit 0 (poscmp_enable=1).
ENC1A/INT
1
I/O
Input B for incremental encoder 1. Can be programmed to provide
position compare output for motor 1 (poscmp_enable=1).
Chip select input of SPI interface, programmable IO in UART mode
Serial clock input of SPI interface, programmable IO in UART mode
Data input of SPI interface, programmable IO in UART mode
Data output of SPI interface (Tristate, enabled with CSN=0), mode
configuration input in UART mode (0 = Normal mode, 1 = Single wire
ring mode – SWIO_P is input, SWIO_N is output)
ENC1B/PP
2
I/O
CSN/IO0
SCK/IO1
SDI/IO2
SDO/RING
3
4
5
8
I/O
I/O
I/O
I/O
Single wire I/O (positive). Serial input in ring mode. Multi-purpose
input in SPI mode or encoder 1 N input.
Single wire I/O (negative) for differential mode. Leave open in non-
differential mode when operating at 5V IO voltage or tie to desired
threshold voltage. Serial output in ring mode. Multi-purpose input in
SPI mode or encoder 2 N input.
SWIOP
(ENC1N)
SWION
(ENC2N)
9
I/O
I/O
10
Clock input. Tie to GND using short wire for internal clock or supply
external clock. The first high signal disables the internal oscillator
until power down.
CLK
11
I
Interface selection input. Tie to GND for SPI mode, tie to VCC_IO for
single wire (UART) interface mode.
Address increment (if tied high) for single wire (UART) mode. General
purpose input in SPI mode
Right reference switch input for motor 2, optional DIR input for
STEP/DIR operation of motor 2 or encoder 2 B input
Left reference switch input for motor 2, optional STEP input for
STEP/DIR operation of motor 2
Right reference switch input for motor 1, optional DIR input for
STEP/DIR operation of motor 1 or encoder 2 A input
Left reference switch input for motor 1, optional STEP input for
STEP/DIR operation of motor 1
Enable input for motor drivers. The power stage becomes switched
off (all motor outputs floating) when this pin becomes driven to a
high level. Tie to GND for normal operation.
SWSEL
12
24
25
I
I
I
I
I
I
I
NEXTADDR
REFR2/DIR2
(ENC2B)
REFL2/STEP2 26
REFR1/DIR1
(ENC2A)
REFL1/STEP1 28
27
DRV_ENN
29
Test mode input. Tie to GND using short wire.
TST_MODE
48
I
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