TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15)
10
2 Pin Assignments
2.1 Package Outline
36
35
34
33
32
31
30
29
28
27
26
25
1
TST_MODE
-
2
CPO
CLK
3
CSN_CFG3
VCC
4
SCK_CFG2
5VOUT
5
SDI_NAI_CFG1
GNDA
TMC5130A-TA
TQFP-48
9mm x 9mm
6
7
-
SDO_NAO_CFG0
REFL_STEP
REFR_DIR
-
AIN_IREF
DRV_ENN_CFG6
SWSEL
8
9
10
11
12
VCC_IO
SWP_DIAG1
SWN_DIAG0
ENCA_DCIN_CFG5
PAD = GNDD
SD_MODE
SPI_MODE
Figure 2.1 TMC5130A-TA package and pinning TQFP-EP 48 (7x7mm body, 9x9mm with leads)
2.2 Signal Descriptions
Pin
Number
Type Function
TST_MODE
1
DI
DI
DI
Test mode input. Tie to GND using short wire.
CLK input. Tie to GND using short wire for internal clock or
supply external clock.
CLK
2
3
4
SPI chip select input (negative active) (SPI_MODE=1) or
CSN_CFG3
SCK_CFG2
(tpu) Configuration input (SPI_MODE=0) (tristate detection).
DI SPI serial clock input (SPI_MODE=1) or
(tpu) Configuration input (SPI_MODE=0) (tristate detection).
SPI data input (SPI_MODE=1) or
Configuration input (SPI_MODE=0) (tristate detection) or
Next address input for single wire interface.
SDI_NAI_
CFG1
DI
(tpu)
5
N.C.
6, 31, 36
7
Unused pins; connect to GND for compatibility to future versions.
SPI data output (tristate) (SPI_MODE=1) or
Configuration input (SPI_MODE=0) (tristate detection) or
Next address output for single wire interface.
SDO_NAO_
CFG0
DIO
(tpu)
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