TMC5161 DATASHEET (Rev. 1.01 / 2018-NOV-20)
12
Pin
Pin
Type Function
Analog supply voltage for 11.5V and 5V regulator. Normally
VSA
4
tied to VS. Provide a 100nF filtering capacitor.
Output of internal 5V regulator. Attach 2.2µF to 10µF ceramic
capacitor to GNDA near to pin for best performance. Output
for VCC supply of the chip.
5VOUT
GNDA
SRAL
6
7
8
Analog GND. Connect to GND plane near pin.
Sense resistor GND connection for phase A. Connect to the
GND side of the sense resistor in order to compensate for
voltage drop on the GND interconnection.
Sense resistor for phase A. Connect to the upper side of the
sense resistor. A Kelvin connection is preferred with high
motor currents. Symmetrical RC-Filtering may be added for
SRAL and SRAH to eliminate high frequency switching spikes
from other drives or switching of coil B.
AI
AI
SRAH
SRBH
10
11
Sense resistor for phase B. Connect to the upper side of the
sense resistor. A Kelvin connection is preferred with high
motor currents. Symmetrical RC-Filtering may be added for
SRBL and SRBH to eliminate high frequency switching spikes
from other drives or switching of coil A.
AI
Sense resistor GND connection for phase B. Connect to the
GND side of the sense resistor in order to compensate for
voltage drop on the GND interconnection.
Test mode input. Tie to GND using short wire.
CLK input. Tie to GND using short wire for internal clock or
supply external clock. Internal clock-fail over circuit protects
against loss of external clock signal.
SRBL
12
13
14
AI
DI
DI
TST_MODE
CLK
SPI chip select input (negative active) (SPI_MODE=1) or
Configuration input (SPI_MODE=0)
SPI serial clock input (SPI_MODE=1) or
CSN_CFG3
SCK_CFG2
15
16
DI
DI
Configuration input (SPI_MODE=0)
SPI data input (SPI_MODE=1) or
SDI_CFG1
17
DI
Configuration input (SPI_MODE=0) or
Next address input (NAI) for single wire interface.
SPI data output (tristate) (SPI_MODE=1) or
SDO_CFG0
REFL_STEP
18
19
DIO
Configuration input (SPI_MODE=0) or
Next address output (NAO) for single wire interface.
Left reference input (for internal ramp generator) or
STEP input when (SD_MODE=1).
Right reference input (for internal ramp generator) or
DIR input (SD_MODE=1).
3.3V to 5V IO supply voltage for all digital pins.
Mode selection input. When tied low, the internal ramp
generator generates step pulses. When tied high, the STEP/DIR
inputs control the driver. SD_MODE=0 and SPI_MODE=0 enable
UART operation.
Mode selection input. When tied low with SD_MODE=1, the
chip is in standalone mode and pins have their CFG functions.
When tied high, the SPI interface is enabled. Integrated pull
down resistor.
DI
DI
REFR_DIR
VCC_IO
20
21
SD_MODE
SPI_MODE
22
23
DI
DI
(pd)
Encoder B-channel input (when using internal ramp generator)
or
dcStep enable input (SD_MODE=1, SPI_MODE=1) – leave open
or tie to GND for normal operation in this mode (no dcStep).
Configuration input (SPI_MODE=0)
ENCB_DCEN_
CFG4
DI
(pd)
24
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