TMC8460 PRELIMINARY, CONFIDENTIAL TARGET, NON-RELEASE VERSION Datasheet (V014 / 2015-Aug-31)
GENERAL PURPOSE IOS
There are up to 8 outputs or up to 8 inputs
Each IO is individually configurable
INCREMENTAL ENCODER UNIT
Incremental encoder inputs (ABN) with configurable counting constant, polarity, N-signal behavior
and latch on N-signal
32 bit count register
STEP & DIRECTION UNIT
Simple internal step rate generator
Configurable step pulse width and polarity
Continuous mode or one-shot mode with configurable step number
Counter for steps that have been done
3-CH PWM
configurable frequency, duty cycle, polarity, dead times, polarity per channel
SPI MASTER INTERFACE
To directly connect to a TMC driver/controller or other SPI slaves
Up to 4 slaves
Configurable speed, mode, datagram width up to 64 bits (longer datagrams are possible)
IRQ / EVENT OUTPUT
Common IRQ signal to indicate various events triggered by the MFCIO block
Mask register to enable/disable certain event triggers
WATCHDOG
Configurable for all inputs and outputs
Outputs will be assigned with configurable level @ watchdog event
Inputs will trigger a watchdog event only
ECAT SoF and PDI SPI Chip Select can be monitored with watchdog as well
EMERGENCY SWITCH INPUT
If used all functional outputs are set to a configurable safe state when the switch is not actively
driven high
Low active: must be pulled high for normal operation if used.
2.2 Configuration Options
The TMC8460 must be configured after power-up for proper operation. The EtherCAT part is automatically
configured using configuration data from the connected I2C EEPROM.
The MFCIO block can also be configured using EEPROM configuration data. The EEPROM must therefore
contain additional configuration data with category ‘1’, which is automatically copied to ESC
configuration RAM at addresses 0x0580:0x05FF.
Another way to configure the MFCIO block is to directly write the configuration bits to this RAM area
using the ECAT or the PDI interface.