TL5001
DETAILED DESCRIPTION(Cont.)
DEAD TIME CONTORL (DTC)
LINEAR INTEGRATED CIRCUIT
DTC provides a means of limiting the output-switch duty cycle to a value less than 100%, which is critical for boost
and flyback converters. A current source generates a reference current (IDT) at DTC that is nominally equal to the
current at the oscillator timing terminal, RT. Connecting a resistor between DTC and GND generates a dead-time
reference voltage (VDT), which the PWM/DTC comparator compares to the oscillator triangle wave as described in
the previous section. Nominally, the maximum duty cycle is 0% when VDT is 0.7V or less and 100% when VDT is
1.3V or greater. Because the triangle wave amplitude is a function of frequency and the source impedance of RT is
relatively high(1250Ω),choosing RDT for a specific maximum duty cycle, D, is accomplished using the following
equation and the voltage limits for the frequency in question as found in Figure 11(Voscmax and Voscmin are the
maximum and minimum oscillator levels):
R
DT
=(Rt +1250)[D(Vosc max-Vosc min)+Vosc min]
Where
R
DT
and Rt are in ohms, D in decimal
Soft start can be implemented by paralleling the DTC resistor with a capacitor (C
DT
) as shown in Figure 2. During
soft start, the voltage at DTC is derived by the following equation:
V
DT
≈I
DT
R
DT
(1-e
(-t/RDTCDT)
)
6 DTC
C
DT
R
DT
UTC
TL5001
Figure 2. Soft- Start Circuit
If the dc-to-dc converter must be in regulation within a specified period of time, the time constant, RDTCDT,
should be t0/3 to t0/5.The UTC
TL5001
remains off unit VDT≈0.7V, the minimum ramp value. CDT is discharged
every time UVLO or SCP becomes active.
UNDERVOLTAGE-LOCKOUT (UVLO) PROTECTION
The undervoltage-lockout circuit turns the output transistor off and resets the SCP latch whenever the supply
voltage drops too low (approximately 3V at 25℃) for proper operation. A hysteresis voltage of 200mV eliminates
false triggering on noise and chattering.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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QW-R103-016,B
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