UTC UC3842B / 3843B LINEAR INTEGRATED CIRCUIT
PARAMETER
Maximum Current Sense Input
Threshold
Power Supply Rejection Ratio
Input Bias Current
Propagation Delay
SYMBOL
Vth
PSRR
I
IB
tPLH(In/O
ut)
V
OL
V
OH
V
OL
(UVLO)
tr
t
f
Vth
V
CC(min)
TEST CONDITIONS
(note 3)
12<=Vcc<=25V (note 3)
Current Sense Input to Output
MIN
0.9
TYP
1.0
70
-2
150
MAX
1.1
UNIT
V
dB
µA
ns
-10
300
Output Section
Output Low Voltage
Output High Level
Output Voltage with UVLO
Activated
Output Voltage Rise Time
Output Voltage Fall Time
Isink=20mA
Isink=200mA
Isource=20mA
Isource=200mA
Vcc=6.0V,Isink=1.0mA
Tj=25°C,C
L
=1nF
Tj=25°C,C
L
=1nF
UTC UC3842B
UTC UC3843B
UTC3842B
UTC3843B
14.5
7.8
8.5
7.0
94
13
12
0.1
1.6
13.5
13.4
0.1
50
50
16
8.4
10
7.6
96
0
0.3
12
36
0.5
17
0.4
2.2
V
V
V
V
V
ns
ns
V
V
V
V
%
%
mA
mA
V
1.1
150
150
17.5
9
11.5
8.2
Under-Voltage Lockout Section
Startup Threshold
Min. Operating Voltage After
Turn-on(Vcc)
PWM Section
Maximum Duty Cycle
Minimum Duty Cycle
DC
(MAX)
DC
(MIN)
Icc+Ic
Total Device
Vcc=6.5V for UC3843B
Vcc=14V for UC3842B
Power Operating Supply Current
Icc+Ic
Note2
Power Supply Zener Voltage
Vz
Icc=25mA
Note 1:Maximum Package power dissipation limits must be observed.
Note 2:Adject Vcc above the Startup threshold before setting to 15V.
Note 3:This parameter is measured at the latch trip point with VFB=0V.
Note 4:Comparator gain is defined as :
∆V
Output Compensation
AV
∆V
Current Sense Input
Power Startup Supply Current
30
UTC
UNISONIC TECHNOLOGIES CO., LTD.
3
QW-R103-012,A