BCM3814x60E10A5yzz
Serial Clock input (SCL) AND Serial Data (SDA) Pins
• High power SMBus specification and SMBus physical layer compatible. Note that optional SMBALERT# is signal not supported.
• PMBusTM command compatible.
• The internal µC requires the use of a flip flop to drive SSTOP. See system diagram section for more details.
SIGNAL TYPE
STATE
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
MIN
TYP MAX UNIT
Electrical Parameters
VIH
VIL
VVDD_IN = 3.3V
2.1
3
V
Input Voltage Threshold
Output Voltage Threshold
VVDD_IN = 3.3V
VVDD_IN = 3.3V
VVDD_IN = 3.3V
Unpowered device
VOL = 0.4V
0.8
V
V
VOH
VOL
0.4
10
V
Leakage current
ILEAK PIN
ILOAD
µA
mA
Signal Sink Current
4
Total capacitive load of
one device pin
Signal Capacitive Load
CI
10
pF
Signal Noise Immunity
Timing Parameters
Operating Frequency
VNOISE_PP
10MHz to 100MHz
300
mV
FSMB
tBUF
tHD:STA
tSU:STA
Idle state = 0Hz
10
400
KHz
µs
Free time between
Stop and Start Condition
1.3
DIGITAL
Regular
Hold time after Start or
Repeated Start condition
First clock is generated
after this hold time
INPUT/OUTPUT
Operation
0.6
0.6
µs
µs
Repeat Start Condition
Setup time
Stop Condition setup time
Data Hold time
tSU:STO
tHD:DAT
tSU:DAT
tTIMEOUT
tLOW
0.6
300
100
25
µs
ns
ns
ms
µs
µs
Data Setup time
Clock low time out
Clock low period
Clock high period
35
1.3
0.6
tHIGH
50
25
Cumulative clock low
extend time
tLOW:SEXT
ms
ns
ns
Measured from
(VIL_MAX 0.15) to (VIH_MIN + 0.15)
Clock or Data Fall time
Clock or Data Rise time
tF
20
20
300
300
tR
0.9 • VVDD_IN_MAX to (VIL_MAX 0.15)
tLOW tR
tF
SCL
VIH
VIL
tHIGH
tSU,DAT
tHD,STA
tHD,DAT
tSU,STA
tSU,STO
SDA
VIH
VIL
tBUF
P
S
S
P
BCM® in a VIA Package
Page 11 of 39
Rev 1.4
09/2016
vicorpower.com
800 927.9474