DG535/536
Vishay Siliconix
DETAILED DESCRIPTION
The DG535/536 are 16-channel single-ended multiplexers
with on-chip address logic and control latches.
The multiplexer connects one of sixteen inputs (S
1
, S
2
through S
16
) to a common output (D) under the control of a
4-bit binary address (A
0
to A
3
). The specific input channel
selected for each address is given in the Truth Table.
All four address inputs have on-chip data latches which are
controlled by the Strobe (ST) input. These latches are
transparent when Strobe is high but they maintain the
chosen address when Strobe goes low. To facilitate easy
microprocessor control in large matrices a choice of three
independent logic inputs (EN, CS and CS) are provided on
chip. These inputs are gated together (see Figure 11) and
only when EN = CS = 1 and CS = 0 can an output switch be
selected. This necessary logic condition is then latched-in
when Strobe (ST) goes low.
Signal
IN
SW1
SW3
Signal
OUT
SW2
Signal
GND
Figure 12. “T” Switch Arrangement
The two second level series switches further improve
crosstalk and help to minimize output capacitance.
The DIS output can be used to signal external circuitry. DIS
is a high impedance to GND when no channel is selected
and a low impedance to GND when any one channel is
selected.
The DG535/536 have extensive applications where any high
frequency video or digital signals are switched or routed.
Exceptional crosstalk and bandwidth performance is
achieved by using n-channel DMOS FETs for the “T” and
series switches.
CS
Latch
A
0
Latch
A
1
Latch
A
2
Latch
A
3
Latch
ST
n+
p
p-
Substrate
GND
n+
Decode Logic
CS
EN
Gate
Source
Drain
Figure 11. CS, CS, EN, ST Control Logic
Break-before-make switching prevents momentary shorting
when changing from one input to another.
The devices feature a two-level switch arrangement whereby
two banks of eight switches (first level) are connected via two
series switches (second level) to a common DRAIN output.
In order to improve crosstalk all sixteen first level switches
are configured as “T” switches (see Figure 12).
With this method SW
2
operates out of phase with SW
1
and
SW
3
. In the on condition SW
1
and SW
3
are closed with SW
2
open whereas in the off condition SW
1
and SW
3
are open
and SW
2
closed. In the off condition the input to SW
3
is
effectively the isolation leakage of SW
1
working into the
on-resistance of SW
2
(typically 200
Ω).
Figure 13. Cross-Section of a Single
DMOS Switch
It can clearly be seen from Figure 13 that there exists a PN
junction between the substrate and the drain/source
terminals.
Should a signal which is negative with respect to the
substrate (GND pin) be connected to a source or drain
terminal, then the PN junction will become forward biased
and current will flow between the signal source and GND.
This effective shorting of the signal source to GND will not
necessarily cause any damage to the device, provided that
the total current flowing is less than the maximum rating, (i.e.,
20 mA).
www.vishay.com
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Document Number: 70070
S-71241–Rev. E, 25-Jun-07
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