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SFH6319T 参数 Datasheet PDF下载

SFH6319T图片预览
型号: SFH6319T
PDF下载: 下载PDF文件 查看货源
内容描述: 高速光耦, 100 kBd的,低输入电流,高增益 [High Speed Optocoupler, 100 kBd, Low Input Current, High Gain]
分类和应用: 光电输出元件
文件页数/大小: 7 页 / 130 K
品牌: VISHAY [ VISHAY TELEFUNKEN ]
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SFH6318T/SFH6319T
Vishay Semiconductors
SWITCHING CHARACTERISTICS
1)
PARAMETER
Propagation delay time to logic
low at output
Propagation delay time to logic
low at output, (Notes 2 and 3)
Propagation delay time to logic
low at output
Propagation delay time to logic
high at output
Propagation delay time to logic
high at output, (Notes 2 and 3)
Propagation delay time to logic
high at output
1)
TEST CONDITION
I
F
= 1.6 mA, R
L
= 2.2 kΩ
I
F
= 0.5 mA, R
L
= 4.7 kΩ
I
F
= 12 mA, R
L
= 270
Ω
I
F
= 1.6 mA, R
L
= 2.2 kΩ
I
F
= 0.5 mA, R
L
= 4.7 kΩ
I
F
= 12 mA, R
L
= 270
Ω
PART
SFH6318T
SFH6319T
SFH6319T
SFH6318T
SFH6319T
SFH6319T
SYMBOL
t
PHL
t
PHL
t
PHL
t
PLH
t
PLH
t
PLH
MIN
TYP.
2.0
6.0
0.6
2.0
4.0
1.5
MAX
10
25
1.0
35
60
7.0
UNIT
µs
µs
µs
µs
µs
µs
Note:
T
amb
= 25 °C, unless otherwise specified.
2)
Pin 7 open.
3)
Using a resistor between pin 5 and 7 will decrease gain and delay time.
I
10
%
Duty Cycl
1/f < 100
µs
1
Pulse
Generator
ZO = 50
Ω
t
r
= 5 ns
I
F
2
8
7
R
L
3
I
F
= Monitor
4
R
m
6
0.1
µF
5
V
O
t
PHL
C L=15pF
V
O
(Non-Saturated
Response)
90
%
10
%
t
f
+5
V
V
(Saturated
Response)
1.5
V
t
PLH
90
%
10
%
t
r
5
V
1.5
V
V
OL
0
5
V
isfh6318t_01
Figure 1. Switching Test Circuit
COMMON MODE TRANSIENT IMMUNITY
PARAMETER
Common mode transient
immunity at logic high level
output, (Notes 1 and 2)
Common mode transient
immunity at logic low level output,
(Notes 1 and 2)
TEST CONDITION
I
F
= 0 mA, R
L
= 2.2 kΩ,
V
CM
= 10 V
P-P
I
F
= 1.6 mA, R
L
= 2.2 kΩ,
V
CM
= 10 V
P-P
PART
SYMBOL
ICM
H
I
MIN
TYP.
1K
MAX
UNIT
V/µs
ICM
L
I
1K
V/µs
Note:
1)
Common mode transient immunity in logic high level is the maximum tolerable (positive) dV
cm
/dt on the leading edge of the common mode
pulse, V
CM
, to assure that the output will remain in a logic high state (i.e. V
O
> 2.0 V) common mode transient immunity in logic low level is the
maximum tolerable (negative) dV
cm
/dt on the trailing edge of the common mode pulse signal, V
CM
, to assure that the output will remain in a logic
low state (i.e.V
O
< 0.8 V).
2)
In applications where dv/dt may exceed 50,000 V/μs (such as state discharge) a series resistor, R
CC
should be included to protect I
C
from
destructively high surge currents. The recommended value is Refer to Figure 2.
R
CC
[(IV)/0.15 I
F
(mA)] kΩ.
www.vishay.com
4
For technical support, please contact: optocoupler.answers@vishay.com
Document Number 83678
Rev. 1.6, 20-Apr-07