T..RIA Series
Medium Power Phase Control Thyristors
(Power Modules), 50 A/70 A/90 A
Vishay High Power Products
BLOCKING
PARAMETER
SYMBOL
IRRM
TEST CONDITIONS
VALUES
15
UNITS
mA
Maximum peak reverse and
off-state leakage current
,
TJ = TJ maximum
IDRM
RMS isolation voltage
VISOL
50 Hz, circuit to base, all terminals shorted, TJ = 25 °C, t = 1 s
3500
500
V
Critical rate of rise of
off-state voltage
(1)
dV/dt
TJ = TJ maximum, linear to 80 % rated VDRM
V/µs
Note
(1)
Available with dV/dt = 1000 V/µs, to complete code add S90 i.e. T90RIA80S90
TRIGGERING
PARAMETER
SYMBOL
TEST CONDITIONS
TJ = TJ maximum, tp ≤ 5 ms
T50RIA T70RIA T90RIA UNITS
Maximum peak gate power
PGM
10
2.5
2.5
10
12
3
12
3
W
Maximum average
gate power
PG(AV)
IGM
TJ = TJ maximum, f = 50 Hz
Maximum peak gate current
3
3
A
V
TJ = TJ maximum, tp ≤ 5 ms
Maximum peak
negative gate voltage
-VGT
10
10
TJ = - 40 °C
4.0
2.5
1.5
250
100
50
4.0
2.5
1.5
270
120
60
4.0
2.5
1.5
270
120
60
Maximum required
DC gate voltage to trigger
VGT
TJ = 25 °C
V
TJ = TJ maximum
TJ = - 40 °C
Anode supply = 6 V,
resistive load; Ra = 1 Ω
Maximum required
DC gate current to trigger
IGT
TJ = 25 °C
mA
TJ = TJ maximum
Maximum gate voltage
that will not trigger
VGD
0.2
5.0
0.2
6.0
0.2
6.0
V
TJ = TJ maximum, rated VDRM applied
Maximum gate current
that will not trigger
IGD
mA
200
180
160
150
200
180
160
150
200
180
160
150
VD = 0.67 rated VDRM, ITM = 2 x rated dI/dt
Ig = 400 mA for T50RIA and Ig = 500 mA for T70RIA/T90RIA;
tr < 0.5 µs, tp ≥ 6 µs
For repetitive value use 40 % non-repetitive
Per JEDEC STD. RS397, 5.2.2.6
Maximum rate of rise of
turned-on current
dI/dt
A/µs
Document Number: 93756
Revision: 03-Jun-08
For technical questions, contact: ind-modules@vishay.com
www.vishay.com
3
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