VIS
Parameter
Symbol
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
A.C. Characteristics (Ta = 0 ~ 70°C, V
DD
= V
DDQ
= 3.3
±
0.3V , V
SS
= V
SSQ
= 0V, unless otherwise noted)
Limits
-7H
Min
CLK cycle time
CL = 3
CL = 2
CLK to valid output delay
CL = 3
CL = 2
CLK high pulse width
CLK low pulse width
Input setup time (all input)
Input hold time (all input)
Output data hold time
CL = 3
CL = 2
CLK to output in low - Z
CLK to output in H - Z
ROW cycle time
ROW active time
RAS to CAS delay
Row precharge time
Row active to active delay
Write recovery time
Transition time
Mode reg. set cycle
Power down exit setup time
Self refresh exit time
Refresh time
t
CK3
t
CK2
t
AC3
t
AC2
t
CH
t
CL
t
IS
t
IH
t
OH3
t
OH2
t
LZ
t
HZ
t
RC
t
RAS
t
RCD
t
RP
t
RRD
t
WR
t
T
t
RSC
t
PDE
t
SRX
t
REF
2.5
2.5
1.5
0.8
2.7
2.7
0
2.7
67.5
45
15
15
14
14
1
14
7
7
64
10
100K
5.4
7.5
7.5
5.4
5.4
2.5
2.5
1.5
0.8
2.7
3
0
2.7
67.5
45
20
20
15
15
1
15
7.5
7.5
64
10
100K
5.4
Max
Min
7.5
10
5.4
6
3
3
2
1
3
3
0
3
70
50
20
20
20
20
1
20
10
10
64
10
100K
6
-7L
Max
Min
10
8
6
6
-8H
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Unit
Document :1G5-0183
Rev.1
Page 8
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
