VIS
I
DD
Specifications
(V
DD
= 3.3V
VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
±
0.3V, T
A
= 0 ~ 70°C)
-6
-7
Max
Min
Max
Min
-8
Max
Unit Note
95
3,4
Description/test condition
Operating Current
, outputs open
t
≥
t
RC RC
(
min
)
Address changed once during t
CK(min)
.
Burst length = 1 (One bank active)
Precharge Standby Current in non power-down
mode
CKE
≥
V
IH
(min)
,
CS
≥
V
IH
(min),
t
CK
=t
CK
(min)
Input signals are changed once during 2 clocks
Precharge Standby Current in non power-down
mode
CKE
≥
V
IH
(min)
, t
CK
=
Symbol
I
DD1
Min
115
105
I
DD2N
40
40
40
3
I
DD2NS
35
35
35
mA
∞
, CLK
≤
V
IL
(max)
I
DD2P
2
2
2
Input signals are stable
Precharge Standby Current in power-down mode
CKE
≤
V
IL
(max)
, t
CK
= t
CK
(min)
Precharge Standby Current in power-down mode
CKE
≤
V
IL
(max)
, t
CK
=
∞
, CLK
≤
V
IL
(max)
I
DD2PS
2
2
2
Active Standby Current in non power-down mode
CKE
≥
V
IH
(min)
, CS
≥
V
IH(min)
, t
CK
= t
CK(min)
Input signals are changed once during 2 clocks
Active Standby Current in non power-down mode
CKE
I
DD3N
50
50
50
3
≥
V
IH
(min)
, t
CK
=
∞
,
CLK
≤
V
IL
(max)
I
DD3NS
40
40
40
Input signals are stable
Active Standby Current in power-down mode
CKE
≤
V
IL
(max)
, t
CK =
t
CK(min)
Active Standby Current in power-down mode
CKE
I
DD3P
I
DD3PS
35
35
35
35
35
35
≤
V
IL
(max)
, t
CK =
∞
,
CLK
≤
V
IL
(max)
Operating Current
(Page burst, and all banks activated)
t
CCD
= t
CCD(min)
, outputs open, gapless data
Refresh Current
t
RC
≥
t
RC
(min)
(t
REF
= 64ms)
Self Refresh Current
CKE
I
DD4
150
140
130
4,5
I
DD5
I
DD6
100
1
90
1
80
1
3
≤
0.2V
Document:1G5-0189
Rev.1
Page 5
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
