VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
VIS
(3/3)
Current
CS RAS CAS WE
Address
Command
DESL
Action
Notes
Write
recovering
H
L
X
H
X
H
X
H
X
X
Nop ® Enter row active after tDPL
Nop ® Enter row active after tDPL
NOP
BST
L
H
H
L
X
Nop ® Enter row active after tDPL
L
L
L
L
L
L
H
H
H
L
L
L
H
L
BA, CA, A10 READ/READA
BA, CA, A10 WRIT/WRITA
Start read, Determine AP
New write, Determine AP
ILLEGAL
8
H
H
L
H
L
BA, RA
BA, A10
X
ACT
3
3
L
PRE/PALL
PEF/SELF
MRS
ILLEGAL
L
H
L
ILLEGAL
L
L
Op - Code
X
ILLEGAL
Write
X
X
X
DESL
Nop ® Enter precharge after tDPL
recovering
with auto
precharge
L
L
H
H
H
H
H
L
X
X
NOP
BST
Nop ® Enter precharge after tDPL
Nop ® Enter precharge after tDPL
L
L
L
L
L
L
H
H
H
L
L
L
H
L
BA, CA, A10 READ/READA
BA, CA, A10 WRIT/WRITA
ILLEGAL
3,8,11
3,11
3,11
3
ILLEGAL
H
H
L
H
L
BA, RA
BA, A10
X
ACT
ILLEGAL
L
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
ILLEGAL
L
L
Op - Code
X
ILLEGAL
Auto
X
X
X
DESL
Nop Enter idle after tRC
L
H
H
X
X
NOP/BST
Nop Enter idle after tRC
ILLEGAL
Refreshing
L
L
L
H
L
L
L
L
H
L
L
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
READ/WRIT
ACT/PRE/PALL ILLEGAL
REF/SELF/MRS ILLEGAL
L
Mode regis-
ter
setting
X
H
H
H
L
X
H
H
L
DESL
Nop ® Enter idle after 2 Clocks
Nop ® Enter idle after 2 Clocks
ILLEGAL
NOP
BST
X
X
READ/WRITE
ILLEGAL
X
ACT/PRE/PALL/ ILLEGAL
REF/SELF/MRS
Note
1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by BankAddress(BA),
depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL
.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks in multi-bank devices.
Document :1G5-0177
Rev.2
Page13
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
