VIS
Operation Mode
Command
State
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note(1), (2))
CKEn-1 CKEn DQM
(7)
BS
A8
A0-7
A9,
A10
V
V
X
X
V
V
V
V
V
V
V
V
X
X
X
X
X
X
CS
RAS CAS
WE
DSF
BankActivate & Masked Write Disable
BankActivate & Masked Write Enable
BankPrecharge
PrechargeAll
Write
Block Write Command
Write and AutoPrecharge
Block Write and AutoPrecharge
Read
Read and AutoPrecharge
Mode Register Set
Special Mode Register Set
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
Idle
(3)
Idle
(3)
Any
Any
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Idle
Idle
(5)
Any
Active
(4)
Any
Idle
Idle
Idle
(SelfRefresh)
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
X
V
V
V
V
V
V
V
X
X
X
X
X
X
X
V
V
L
H
L
L
H
H
L
H
L
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
L
L
H
H
H
H
H
H
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
H
H
H
L
L
L
L
L
L
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
H
L
L
L
L
L
L
H
H
L
L
H
L
X
H
H
X
H
X
X
H
X
X
H
X
X
L
H
L
L
L
H
L
H
L
L
L
H
X
L
X
L
L
X
X
X
X
L
X
X
L
X
X
Clock Suspend Mode Entry
Power Down Mode Entry
Active
Any
(6)
Active
Any
(Power-
Down)
Active
Active
H
H
L
L
X
X
X
X
X
X
X
X
X
H
L
Clock Suspend Mode Exit
Power Down Mode Exit
L
L
H
H
X
X
X
X
X
X
X
X
X
H
L
Data Write/Output Enable
Data Write/Output Disable
H
H
X
X
L
H
X
X
X
X
X
X
X
X
Note: 1. V = Valid X = Don’t Care L = Low level H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. The Special Mode Register Set is also available in Row Active State.
6. Power Down Mode can not entry in the burst operation.
When this command assert in the burst cycle, device state is clock suspend mode.
7. DQM0-3
Document:
Rev.1
Page 5
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
