W25Q64FVSFIG 参数 Datasheet PDF下载

W25Q64FV

7.1.10

Quad Enable (QE)

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI

and QPI operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are

enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD

functions are disabled.

QE bit is required to be set to a 1 before issuing an “Enable QPI (38h)” to switch the device from

Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI mode,

QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE bit from a

“1” to a “0”.

WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during

standard SPI or Dual SPI operation, the QE bit should never be set to a 1.

S7

SRP0

STATUS REGISTER PROTECT 0

(non-volatile)

SECTOR PROTECT

(non-volatile)

TOP/BOTTOM PROTECT

(non-volatile)

BLOCK PROTECT BITS

(non-volatile)

WRITE ENABLE LATCH

ERASE/WRITE IN PROGRESS

S6

SEC

S5

TB

S4

BP2

S3

BP1

S2

BP0

S1

S0

WEL BUSY

Figure 4a. Status Register-1

S15

SUS

SUSPEND STATUS

COMPLEMENT PROTECT

(non-volatile)

SECURITY REGISTER LOCK BITS

(non-volatile OTP)

RESERVED

QUAD ENABLE

(non-volatile)

STATUS REGISTER PROTECT 1

(non-volatile)

S14

CMP

S13

LB3

S12

LB2

S11

LB1

S10

(R)

S9

QE

S8

SRP1

Figure 4b. Status Register-2

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Publication Release Date: December 19, 2011

Revision D