W681512
TFS
FST
BCLKT
PCMT
TFSFH
TFSRS
TFSRH
-1
TBCKH
TBCKL
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
TBCK
THID
TBDTD
TBDTD
THID
TBDTD
TBDTD
D7 D6 D5
D4 D3 D2 D1 D0
LSB
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
MSB
TDRS
TDRH
TDRS
TDRH
D7
PCMR
D6 D5
D4 D3 D2 D1 D0
LSB
D7 D6 D5 D4 D3 D2
MSB
D1 D0
MSB
LSB
BCH = 0
BCH = 1
B1 Channel
B2 Channel
Figure 8.3 IDL PCM Timing
SYMBOL DESCRIPTION
MIN
---
TYP
MAX
---
UNIT
kHz
kHz
ns
1/TFS
1/TBCK
TBCKH
TBCKL
TFSRH
FST Frequency
8
BCLKT Frequency
256
50
---
---
---
---
4096
---
BCLKT HIGH Pulse Width
BCLKT LOW Pulse Width
50
---
ns
BCLKT –1 Falling Edge to FST Rising Edge
Hold Time
20
---
ns
TFSRS
TFSFH
TBDTD
THID
FST Rising Edge to BCLKT 0 Falling edge
Setup Time
60
20
10
10
---
---
---
---
---
---
60
50
ns
ns
ns
ns
BCLKT 0 Falling Edge to FST Falling Edge
Hold Time
BCLKT Rising Edge to Valid PCMT Delay
Time
Delay Time from the BCLKT 8 Falling Edge
(B1 channel) or BCLKT 18 Falling Edge (B2
Channel) to PCMT Output High Impedance
TDRS
TDRH
Valid PCMR to BCLKT Falling Edge Setup
Time
20
75
---
---
---
---
ns
ns
PCMR Hold Time from BCLKT Falling Edge
Table 8.3 IDL PCM Timing Parameters
Publication Release Date: April, 2007
Revision C14
- 17 -
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