W78C32C/W78C032C
6.3.2
Program Fetch Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low
Address Hold after ALE Low
ALE Low to
PSEN
Low
PSEN
Low to Data Valid
T
AAS
T
AAH
T
APL
T
PDA
T
PDH
T
PDZ
T
ALW
T
PSW
1 T
CP
-Δ
1 T
CP
-Δ
1 T
CP
-Δ
-
0
0
2 T
CP
-Δ
3 T
CP
-Δ
-
-
-
-
-
-
2 T
CP
3 T
CP
-
-
-
2 T
CP
1 T
CP
1 T
CP
-
-
nS
nS
nS
nS
nS
nS
nS
nS
4
1, 4
4
2
3
Data Hold after
PSEN
High
Data Float after
PSEN
High
ALE Pulse Width
4
4
PSEN
Pulse Width
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
CP
.
3. Data have been latched internally prior to
PSEN
going high.
4. "Δ"
( due to buffer driving delay and wire loading) is 20 nS.
6.3.3
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
ALE Low to
RD
Low
RD
Low to Data Valid
T
DAR
T
DDA
T
DDH
T
DDZ
T
DRD
3 T
CP
-Δ
-
0
0
6 T
CP
-Δ
-
-
-
-
6 T
CP
3 T
CP+
Δ
4 T
CP
2 T
CP
2 T
CP
-
nS
nS
nS
nS
nS
1, 2
1
Data Hold after
RD
High
Data Float after
RD
High
RD
Pulse Width
2
Notes:
1. Data memory access time is 8 T
CP
.
2. "
Δ
" (due to buffer driving delay and wire loading) is 20 nS.
- 10 -
WINBOND [ WINBOND ]
