W78LE365/W78L365A
XICON - external interrupt control (C0H)
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt information:
INTERRUPT SOURCE
VECTOR
ADDRESS
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
EDGE/LEVEL
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
Timer/Counter 2
External Interrupt 2
External Interrupt 3
P4CONB (C3H)
BIT
NAME
03H
0BH
13H
1BH
23H
2BH
33H
3BH
0 (highest)
1
2
3
4
5
6
7 (lowest)
IE.0
IE.1
IE.2
IE.3
IE.4
IE.5
XICON.2
XICON.6
TCON.0
-
TCON.2
-
-
-
XICON.0
XICON.3
FUNCTION
00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
7, 6
P43FUN1 10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
P43FUN0
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The
address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.
- 11 -
Publication Release Date: January 10, 2007
Revision A7
WINBOND [ WINBOND ]
