W83195BR-118/W83195BG-118
STEPLESS FOR INTEL 915/945 CHIPSETS
4. BLOCK DIAGRAM
4 8 M H z
P L L 2
2 4 _ 4 8 M H z
D iv id e r
D O T T
D O T C
2
X T A L
X IN
R E F 0 :1
O S C
X O U T
2
C P U T 0 :1
C P U C 0 :1
2
P L L 1
S p re a d
V C O C L K
S R C T
S R C C
S p e c tru m
5
5
P C IE T 0 :4
P C IE C 0 :4
D iv id e r
M /N /R a tio
R O M
3
P C I_ F 0 :2
P C I 0 :5
F S (0 :2 )
V T T _ P W R G D #
& S E L 2 4 _ 4 8 #
L a tc h
& P O R
6
C o n tro l
L o g ic
P D
R E S E T #
4 7 5
& C o n fig
R e g is te r
*S D A T A
*S C L K
I2 C
In te rfa c e
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL
DESCRIPTION
IN
INtp120k
INtd120k
OUT
OD
Input
Latched input at power up, internal 120kΩ pull up.
Latched input at power up, internal 120kΩ pull down.
Output
Open Drain
I/OD
#
Bi-directional Pin, Open Drain.
Active Low
*
Internal 120kΩ pull-up
&
Internal 120 kΩ pull-down
Publication Release Date: May 2006
Revision 0.81
- 3 -
WINBOND [ WINBOND ]
