WM7230
6.
Preliminary Technical Data
SLEEP Mode is enabled when the CLK input is below the CLK Sleep Frequency noted above. This is a power-saving
mode. Normal operation resumes automatically when the CLK input is above the CLK Sleep Frequency. Note that the
VDD supply is still required in SLEEP mode.
AUDIO INTERFACE TIMING
t
CY
CLK
(input)
DAT
(LRSEL = 1)
t
L_EN
DAT
(LRSEL = 0)
t
R_EN
t
L_DIS
t
R_DIS
DAT is high-impedance (hi-z) when not outputting data
Figure 1 Digital Microphone Interface Timing
Test Conditions
The following timing information is valid across the full range of recommended operating conditions.
PARAMETER
Digital Microphone Interface Timing
CLK cycle time
CLK duty cycle
DAT enable from rising CLK edge (LRSEL = 1)
DAT disable from falling CLK edge (LRSEL = 1)
DAT enable from falling CLK edge (LRSEL = 0)
DAT disable from rising CLK edge (LRSEL = 0)
Notes:
1.
SYMBOL
t
CY
t
L_EN
t
L_DIS
t
R_EN
t
R_DIS
MIN
308
60:40
TYP
MAX
1000
40:60
UNIT
ns
ns
18
16
18
16
ns
ns
ns
The DAT output is high-impedance when not outputting data; this enables the outputs of two microphones to be
connected together with the data from one microphone interleaved with the data from the other. (The microphones
must be configured to transmit on opposite channels in this case.)
2.
In a typical configuration, the Left channel is transmitted following the rising CLK edge (LRSEL = 1). In this case, the
Left channel should be sampled by the receiving device on the falling CLK edge,
3.
Similarly, the Right channel is typically transmitted following the falling CLK edge (LRSEL = 0). In this case, the Right
channel should be sampled by the receiving device on the rising CLK edge.
w
PTD, Rev 2.4, October 2012
6
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
