X28HT010
CE
Controlled Write Cycle
tWC
ADDRESS
tAS
CE
tOES
OE
tOEH
tCS
WE
tDV
DATA IN
DATA VALID
tDS
DATA OUT
HIGH Z
6613 FHD F07
tAH
tCW
tWPH
tCH
tDH
Page Write Cycle
OE
(5)
CE
tWP
WE
tWPH
ADDRESS *
(6)
tBLC
I/O
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
LAST BYTE
BYTE n+2
tWC
6613 FHD F08
*For each successive write within the page write operation, A8–A16 should be the same or
writes to an unknown address could occur.
Notes:
(5) Between successive byte writes within a page write operation,
OE
can be strobed LOW: e.g. this can be done with
CE
and
WE
HIGH to fetch data from another memory device within the system for the next write; or with
WE
HIGH and
CE
LOW effectively
performing a polling operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must
conform to either the
CE
or
WE
controlled write cycle timing.
8