欢迎访问ic37.com |
会员登录 免费注册
发布采购

X84041SI-3 参数 Datasheet PDF下载

X84041SI-3图片预览
型号: X84041SI-3
PDF下载: 下载PDF文件 查看货源
内容描述: 微型端口节电器E2PROM [Micro Port Saver E2PROM]
分类和应用: 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 13 页 / 69 K
品牌: XICOR [ XICOR INC. ]
 浏览型号X84041SI-3的Datasheet PDF文件第2页浏览型号X84041SI-3的Datasheet PDF文件第3页浏览型号X84041SI-3的Datasheet PDF文件第4页浏览型号X84041SI-3的Datasheet PDF文件第5页浏览型号X84041SI-3的Datasheet PDF文件第6页浏览型号X84041SI-3的Datasheet PDF文件第7页浏览型号X84041SI-3的Datasheet PDF文件第8页浏览型号X84041SI-3的Datasheet PDF文件第9页  
A
PPLICATION
N
OTES AND
D
EVELOPMENT
S
YSTEM
A V A I L A B L E
AN10
X84041
• AN17 • AN57 • XK84
4K
X84041
Micro Port Saver E
2
PROM
MPS
E
2
PROM
FEATURES
• Direct Interface to Micros
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• 3.3Mbps data transfer rate
• Low Power CMOS
—2.7V to 5.5V Operation
—Standby Current Less than 50
µ
A
—Active Current Less than 1mA
• 45ns Read Access Time
• 8-Byte Page Write Mode
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• 8-Lead PDIP, 8-Lead SOIC, and
14-Lead TSSOP Packages
DESCRIPTION
The X84041 Micro Port Saver is a 4096-bit CMOS
E
2
PROM designed for a direct interface to port limited
microcontroller or I/O limited microprocessor designs.
The X84041 provides all of the benefits of serial memo-
ries, such as low cost, low power, low voltage operation,
and small package size, while featuring higher data
transfer rates and reduced interface code requirements—
without the need for a dedicated serial bus. The X84041
is organized as a 512 x 8, but is also suitable in 16-bit or
32-bit environments, due to the bit serial nature of the
interface.
The X84041 directly connects to the processor bus and
communicates over a single data line using a sequence
of standard bus read and write operations. This elimi-
nates the need for dedicated port pins, parallel to serial
converters, complicated ASIC implementations, or other
glue logic, lowering system cost.
BLOCK DIAGRAM
WP
8
7
X84041
6
5
VCC
NC
OE
WE
2704 ILL F01.2
PIN CONFIGURATION
DIP/SOIC
CE
I/O
WP
VSS
1
2
3
4
H.V. GENERATION
TIMING & CONTROL
CE
OE
WE
I/O
COMMAND
DECODE
AND
CONTROL
LOGIC
X
DEC
EEPROM
ARRAY
512 x 8
TSSOP
CE
I/O
NC
NC
NC
WP
V
SS
1
2
3
5
6
7
14
13
12
10
9
8
V
CC
NC
NC
NC
NC
OE
WE
2704 ILL F02a.1
Y DECODE
DATA REGISTER
2704 ILL F02
4
X84041
11
PIN NAMES
I/O
CE
OE
WE
WP
V
CC
V
SS
NC
Data Input/Output
Chip Enable Input
Output Enable Input
Write Enable Input
Write Protect Input
Supply Voltage
Ground
No Connect
2704 PGM T01
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
2704-4.4 6/12/96 T3/C1/D0 NS
1
Characteristics subject to change without notice