X9251
Figure 2. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
0
0
A1
A0
I3
I2
I1
I0
RB RA P1
P0
ID3 ID2 ID1 ID0
Device ID
Internal
Address
Instruction
Opcode
Register DCP/WCR
Address Address
Figure 3. Three-Byte Instruction Sequence SPI Interface; Write Case
CS
SCK
SI
0
0
0
0
A1 A0
Internal
Address
I3 I2
I1
I0
RB RA P1 P0
Register DCP/WCR
Address Address
D7 D6 D5 D4 D3 D2 D1 D0
Data for WCR[7:0] or DR[7:0]
0
1
0
1
ID3 ID2 ID1 ID0
Device ID
Instruction
Opcode
Figure 4. Three-Byte Instruction Sequence SPI Interface, Read Case
CS
SCK
SI
0
0
0
0
A1 A0
Internal
Address
I3
I2
I1
I0
RB RA P1 P0
Register DCP/WCR
Address Address
0
1
0
1
X
X
X
X
X
X
X
X
ID3 ID2 ID1 ID0
Device ID
Don’t Care
Instruction
Opcode
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
or
Data Register Bit [7:0]
REV 1.3.3 2/10/04
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Characteristics subject to change without notice.
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