X9428
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IH
V
IL
V
OL
Parameter
V
CC
supply current
(nonvolatile write)
V
CC
supply current
(move wiper, write, read)
V
CC
current (standby)
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
Min.
Typ.
Max.
1
100
1
10
10
Unit
mA
µA
µA
µA
µA
V
V
V
Test Conditions
f
SCL
= 400kHz, SDA = Open,
Other Inputs = V
SS
f
SCL
= 400kHz, SDA = Open,
Other Inputs = V
SS
SCL = SDA = V
CC
, Addr. = V
SS
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
V
CC
x 0.7
–0.5
V
CC
x 0.5
V
CC
x 0.1
0.4
I
OL
= 3mA
Notes:
(1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R
H
—R
L
)/63, single pot
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
CAPACITANCE
Symbol
C
I/O
(5)
C
IN
(5)
Test
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3, and SCL)
Max.
8
6
Unit
pF
pF
Test Conditions
V
I/O
= 0V
V
IN
= 0V
POWER-UP TIMING
Symbol
t
PUR
(6)
t
PUW
(6)
t
R
V
CC
(7)
Parameter
Power-up to initiation of read operation
Power-up to initiation of write operation
V
CC
Power up ramp rate
Min.
Typ.
Max.
1
5
Unit
ms
ms
V/msec
0.2
50
POWER-UP AND POWER-DOWN
There are no restrictions on the power-up or power-down sequencing of the bias supplies V
CC
, V+, and V- provided
that all three supplies reach their final values within 1msec of each other. However, at all times, the voltages on the
potentiometer pins must be less than V+ and more than V–. The recall of the wiper position from nonvolatile
memory is not in effect until all supplies reach their final value.
Notes:
(5) This parameter is periodically sampled and not 100% tested
(6) t
PUR
and t
PUW
are the delays required from the time the third (last) power supply (V
CC
, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
REV 1.1.5 7/8/03
www.xicor.com
Characteristics subject to change without notice.
12 of 20
XICOR [ XICOR INC. ]
