R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 5:
Minimum Power On Current Required for Virtex-II Devices
Device (mA)
XC2V40, XC2V80,
XC2V250, XC2V500
I
CCINTMIN
I
CCAUXMIN
I
CCOMIN
200
100
50
XC2V1000
250
100
50
XC2V1500
350
100
100
XC2V2000
400
100
100
XC2V3000
500
100
100
XC2V4000
650
100
100
XC2V6000
800
100
100
XC2V8000
1100
100
100
Notes:
1. Values specified for power on current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial Grade
values by 1.25.
2. I
CCOMIN
values listed here apply to the entire device (all banks).
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is sessential.
Consult Xilinx Application Note
for detailed infor-
mation on power distribution system design.
V
CCAUX
powers critical resources in the FPGA. Thus,
V
CCAUX
is especially susceptible to power supply noise.
Changes in V
CCAUX
voltage outside of 200 mV peak to peak
should take place at a rate no faster than 10 mV per milli-
second. Techniques to help reduce jitter and period distor-
tion are provided in Xilinx Answer Record 13756, available
at
.
V
CCAUX
can share a power plane with 3.3V V
CCO
, but only if
V
CCO
does not have excessive noise. Using simultaneously
switching output (SSO) limits are essential for keeping
power supply noise to a minimum. Refer to
, “Man-
aging Ground Bounce in Large FPGAs,” to determine the
number of simultaneously switching outputs allowed per
bank at the package level.
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages.
Values for I
OL
and I
OH
are guaranteed over the recom-
mended operating conditions at the V
OL
and V
OH
test
points. Only selected standards are tested. These are cho-
Table 6:
DC Input and Output Levels
Input/Output
Standard
LVTTL
(1)
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI–X
GTLP
GTL
HSTL I
HSTL II
HSTL III
HSTL IV
sen to ensure that all standards meet their specifications.
The selected standards are tested at minimum V
CCO
with
the respective V
OL
and V
OH
voltage levels shown. Other
standards are sample tested.
V
IL
V, Min
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
V
IH
V, Min
2.0
2.0
1.7
65% V
CCO
65% V
CCO
50% V
CCO
50% V
CCO
Note 2
V
REF
+ 0.1
V
REF
+ 0.05
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
OL
V, Max
3.6
3.6
2.7
1.95
1.7
V
CCO
+ 0.5
V
CCO
+ 0.5
Note 2
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
OH
V, Min
2.4
V
CCO
– 0.4
V
CCO
– 0.4
V
CCO
– 0.4
V
CCO
– 0.4
90% V
CCO
90% V
CCO
Note 2
n/a
n/a
V
CCO
– 0.4
V
CCO
– 0.4
V
CCO
– 0.4
V
CCO
– 0.4
I
OL
mA
24
24
24
16
16
Note 2
Note 2
Note 2
36
40
8
16
24
48
I
OH
mA
– 24
– 24
– 24
– 16
– 16
Note 2
Note 2
Note 2
n/a
n/a
–8
– 16
–8
–8
V, Max
0.8
0.8
0.7
35% V
CCO
35% V
CCO
30% V
CCO
30% V
CCO
Note 2
V
REF
– 0.1
V
REF
– 0.05
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V, Max
0.4
0.4
0.4
0.4
0.4
10% V
CCO
10% V
CCO
Note 2
0.6
0.4
0.4
0.4
0.4
0.4
DS031-3 (v3.5) November 5, 2007
Product Specification
Module 3 of 4
4
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