R
Spartan-3 FPGA Family: Pinout Descriptions
Table 10: Pin Behavior After Power-Up, During Configuration
Configuration Mode Settings <M2:M1:M0>
Serial Modes SelectMap Parallel Modes
Bitstream
Configuration
Option
Master
<0:0:0>
Slave
<1:1:1>
Master
<0:1:1>
Slave
<1:1:0>
JTAG Mode
<1:0:1>
Pin Name
I/O: General-purpose I/O pins
IO
UnusedPin
UnusedPin
IO_Lxxy_#
DUAL: Dual-purpose configuration pins
IO_Lxxy_#/
DIN/D0
DIN (I)
DIN (I)
D0 (I/O)
D1 (I/O)
D0 (I/O)
D1 (I/O)
Persist
UnusedPin
IO_Lxxy_#/
D1
Persist
UnusedPin
IO_Lxxy_#/
D2
D2 (I/O)
D2 (I/O)
Persist
UnusedPin
IO_Lxxy_#/
D3
D3 (I/O)
D3 (I/O)
Persist
UnusedPin
IO_Lxxy_#/
D4
D4 (I/O)
D4 (I/O)
Persist
UnusedPin
IO_Lxxy_#/
D5
D5 (I/O)
D5 (I/O)
Persist
UnusedPin
IO_Lxxy_#/
D6
D6 (I/O)
D6 (I/O)
Persist
UnusedPin
IO_Lxxy_#/
D7
D7 (I/O)
D7 (I/O)
Persist
UnusedPin
IO_Lxxy_#/
CS_B
CS_B (I)
RDWR_B (I)
BUSY (O)
CS_B (I)
RDWR_B (I)
BUSY (O)
Persist
UnusedPin
IO_Lxxy_#/
RDWR_B
Persist
UnusedPin
IO_Lxxy_#/
DOUT (O)
DOUT (O)
Persist
BUSY/DOUT
UnusedPin
IO_Lxxy_#/
INIT_B
INIT_B (I/OD) INIT_B (I/OD) INIT_B (I/OD) INIT_B (I/OD)
UnusedPin
DCI: Digitally Controlled Impedance reference resistor input pins
IO_Lxxy_#/
VRN_#
UnusedPin
IO/VRN_#
UnusedPin
UnusedPin
IO_Lxxy_#/
VRP_#
IO/VRP_#
UnusedPin
16
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DS099-4 (v1.5) July 13, 2004
Product Specification
XILINX [ XILINX, INC ]
