R
Spartan-3 FPGA Family: Pinout Descriptions
Table 4: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes
Pin
Name
Direction
Description
Configuration Data Port (high nibble):
D0,
Input during
configuration
D1,
D2,
D3
Collectively, the D0-D7 pins are the byte-wide configuration data port for the Parallel
(SelectMAP) configuration modes. Configuration data is synchronized to the rising edge of
CCLK clock signal.
Outputduring
readback
The D0-D3 pins are the high nibble of the configuration data byte and located in Bank 4 and
powered by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
Configuration Data Port (low nibble):
D4,
D5,
D6,
D7
Input during
configuration
The D4-D7 pins are the low nibble of the configuration data byte. However, these signals are
located in Bank 5 and powered by VCCO_5.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
Outputduring
readback
Chip Select for Parallel Mode Configuration:
CS_B
Input
Assert this pin Low, together with RDWR_B to write a configuration data byte from the D0-D7
bus to the FPGA on a rising CCLK edge.
During Readback, assert this pin Low, along with RDWR_B High, to read a configuration data
byte from the FPGA to the D0-D7 bus on a rising CCLK edge.
This signal is located in Bank 5 and powered by VCCO_5.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
CS_B
Function
0
1
FPGA selected. SelectMAP inputs are valid on the next rising edge of CCLK.
FPGA deselected. All SelectMAP inputs are ignored.
DS099-4 (v1.5) July 13, 2004
Product Specification
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