R
XC95288XV High-Performance CPLD
V
TEST
R
1
Device Output
R
2
C
L
Output Type
V
CCIO
3.3V
2.5V
1.8V
V
TEST
3.3V
2.5V
R
1
320Ω
250Ω
R
2
360Ω
660Ω
C
L
35 pF
35 pF
DS052_03_041200
Figure 3:
AC Load Circuit
Internal Timing Parameters
XC95288XV-5
Symbol
Buffer Delays
T
IN
T
GCK
T
GSR
T
GTS
T
OUT
T
EN
T
PTCK
T
PTSR
T
PTTS
T
PDI
T
SUI
T
HI
T
ECSU
T
ECHO
T
COI
T
AOI
T
RAI
T
LOGI
T
LOGILP
T
F
T
PTA
T
PTA2
T
SLEW
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable delay
Product term clock delay
Product term set/reset delay
Product term 3-state delay
Combinatorial logic propagation delay
Register setup time
Register hold time
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
Internal low power logic delay
FastCONNECT II feedback delay
Incremental product term allocator delay
Adjacent macrocell p-term allocator delay
Slew-rate limited delay
-
-
-
-
-
-
-
-
-
-
2.0
1.5
2.0
1.5
-
-
5.0
-
-
-
-
-
0.7
5.7
1.6
0.7
0.3
2.0
1.2
2.0
4.0
2.1
0
1.7
0.7
5.0
0.2
-
-
-
-
0.2
5.9
-
-
-
-
-
-
-
-
-
-
2.6
2.2
2.6
2.2
-
-
7.5
-
-
-
-
-
-
1.4
6.4
3.5
0.8
0.3
2.3
1.5
3.1
5.0
2.5
0
2.4
1.4
7.2
1.3
-
-
-
-
0.5
6.4
-
-
-
-
-
-
-
-
-
-
3.0
3.5
3.0
3.5
-
-
10.0
-
-
-
-
-
3.5
1.8
4.5
7.0
3.0
0
2.7
1.8
7.5
1.7
-
-
-
-
1.0
7.0
-
1.8
7.3
4.2
1.0
0.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min
Max
XC95288XV-7
Min
Max
XC95288XV-10
Min
Max
Units
Product Term Control Delays
Internal Register and Combinatorial Delays
Feedback Delays
Time Adders
-
3.0
Advance Information
4.0
-
4.5
Preliminary Information
Notes:
1.
Please contact Xilinx for up-to-date information on advance specifications.
DS050 (v2.2) August 27, 2001
Advance Product Specification
1-800-255-7778
5
XILINX [ XILINX, INC ]
