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XC95288XV High-Performance
CPLD
0
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DS050 (v3.0) June 25, 2007
Product Specification
Note: This product is being discontinued.
You cannot
order parts after May 14, 2008. Xilinx recommends replac-
ing XC95288XV devices with equivalent XC95288XL
devices in all designs as soon as possible. Recommended
replacements are pin compatible, however require a V
CC
change to 3.3V, and a recompile of the design file. In addi-
tion, there is no 1.8V I/O support, and only one output bank
is supported. See
for details regarding this dis-
continuation, including device replacement recomendations
for the XC95288XV CPLD.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
P
TOTAL
= P
INT
+ P
IO
= I
CCINT
x V
CCINT
+ P
IO
Separating internal and I/O power here is convenient
because XC9500XV CPLDs also separate the correspond-
ing power pins. P
IO
is a strong function of the load capaci-
tance driven, so it is handled by I = CVf. I
CCINT
is another
situation that reflects the actual design considered and the
internal switching speeds. An estimation expression for
I
CCINT
(taken from simulation) is:
I
CCINT
(mA) = MC
HS
(0.122 X PT
HS
+ 0.238) + MC
LP
(0.042 x
PT
LP
+ 0.171) + 0.04(MC
HS
+ MC
LP
) x f
MAX
x MC
TOG
where:
MC
HS
= # macrocells used in high speed mode
MC
LP
= #macrocells used in low power mode
PT
HS
= average p-terms used per high speed macrocell
PT
LP
= average p-terms used over low power macrocell
f
MAX
= max clocking frequency in the device
MC
TOG
= % macrocells toggling on each clock (12% is
frequently a good estimate
This calculation was derived from laboratory measurements
of an XC9500XV part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
CC
value varies with the design application and should be veri-
fied during normal system operation.
shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
Features
•
•
288 macrocells with 6,400 usable gates
Available in small footprint packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 280-pin CSP (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
Optimized for high-performance 2.5V systems
- Low power operation
- Multi-voltage operation
Advanced system features
- In-system programmable
- Four separate output banks
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold ciruitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- 20 year data retention
- ESD protection exceeding 2,000V
•
•
•
•
•
•
Description
The XC95288XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns.
© 2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS050 (v3.0) June 25, 2007
Product Specification
1
XILINX [ XILINX, INC ]
