R
XC9536XL High Performance CPLD
Internal Timing Parameters
XC9536XL-5
Symbol
Buffer Delays
T
IN
T
GCK
T
GSR
T
GTS
T
OUT
T
EN
T
PTCK
T
PTSR
T
PTTS
T
PDI
T
SUI
T
HI
T
ECSU
T
COI
T
AOI
T
RAI
T
LOGI
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable delay
-
-
-
-
-
-
1.5
1.1
2.0
4.0
2.0
0
-
-
-
-
-
-
2.3
1.5
3.1
5.0
2.5
0
-
-
-
-
-
-
3.5
1.8
4.5
7.0
3.0
0
ns
ns
ns
ns
ns
ns
Parameter
Min
Max
XC9536XL-7
Min
Max
XC9536XL-10
Min
Max
Units
Product Term Control Delays
Product term clock delay
Product term set/reset delay
Product term 3-state delay
-
-
-
1.6
1.0
5.5
-
-
-
2.4
1.4
7.2
-
-
-
2.7
1.8
7.5
ns
ns
ns
Internal Register and Combinatorial Delays
Combinatorial logic propagation delay
Register setup time
Register hold time
Register clock enable setup time
-
2.3
1.4
2.3
1.4
-
-
5.0
-
-
-
1.0
5.0
1.9
0.5
-
-
-
-
0.4
6.0
-
2.6
2.2
2.6
2.2
-
-
7.5
-
-
-
1.4
6.4
3.5
1.3
-
-
-
-
0.5
6.4
-
3.0
3.5
3.0
3.5
-
-
10.0
-
-
-
1.8
7.3
4.2
1.7
-
-
-
-
1.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
ECHO
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
T
LOGILP
Internal low power logic delay
Feedback Delays
T
F
T
PTA
FastCONNECT II feedback delay
Time Adders
Incremental product term allocator delay
-
-
0.7
3.0
-
-
0.8
4.0
-
-
1.0
4.5
ns
ns
T
SLEW
Slew-rate limited delay
DS058 (v1.2) June 25, 2001
Preliminary Product Specification
1-800-255-7778
5
XILINX [ XILINX, INC ]
