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XC9500XL High-Performance CPLD
Family Data Sheet
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DS054 (v2.5) May 22, 2009
Product Specification
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-
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-
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•
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin with local
inversion
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold circuitry on all user pin inputs
Supports hot-plugging capability
Full IEEE Std 1149.1 boundary-scan (JTAG)
support on all devices
36 to 288 macrocells, with 800 to 6400 usable
gates
Features
•
Optimized for high-performance 3.3V systems
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•
5 ns pin-to-pin logic delays, with internal system
frequency up to 208 MHz
Small footprint packages including VQFPs, TQFPs
and CSPs (Chip Scale Package)
Pb-free available for all packages
Lower power operation
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
3.3V or 2.5V output capability
Advanced 0.35 micron feature size CMOS
FastFLASH technology
In-system programmable
Superior pin-locking and routability with
FastCONNECT II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
•
Four pin-compatible device densities
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Advanced system features
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•
•
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Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
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10,000 program/erase cycles endurance rating
20 year data retention
Pin-compatible with 5V core XC9500 family in common
package footprints
Table 1:
XC9500XL Device Family
XC9536XL
Macrocells
Usable Gates
Registers
T
PD
(ns)
T
SU
(ns)
T
CO
(ns)
f
SYSTEM
(MHz)
36
800
36
5
3.7
3.5
178
XC9572XL
72
1,600
72
5
3.7
3.5
178
XC95144XL
144
3,200
144
5
3.7
3.5
178
XC95288XL
288
6,400
288
6
4.0
3.8
208
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countries. All other trademarks are the property of their respective owners.
DS054 (v2.5) May 22, 2009
Product Specification
1
XILINX [ XILINX, INC ]
