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XCR3032XL-7CS48I 参数 Datasheet PDF下载

XCR3032XL-7CS48I图片预览
型号: XCR3032XL-7CS48I
PDF下载: 下载PDF文件 查看货源
内容描述: XCR3032XL 32宏单元CPLD [XCR3032XL 32 Macrocell CPLD]
分类和应用:
文件页数/大小: 9 页 / 219 K
品牌: XILINX [ XILINX, INC ]
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0
R
XCR3032XL 32 Macrocell CPLD
0
14
DS023 (v2.2) September 15, 2008
Product Specification
Features
Low power 3.3V 32 macrocell CPLD
4.5 ns pin-to-pin logic delays
System frequencies up to 213 MHz
32 macrocells with 750 usable gates
Available in small footprint packages
- 48-ball CS BGA (36 user I/O pins)
- 44-pin VQFP (36 user I/Os)
Optimized for 3.3V systems
- Ultra-low power operation
- Typical Standby Current of 17
μA
at 25°C
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power (FZP) CMOS technology
- 3.3V PCI electrical specification compatible
outputs (no internal clamp diode on any input or
I/O, no minimum clock input capacitance)
Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
2.7V to 3.6V supply voltage at industrial temperature
range
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
Refer to the CoolRunner XPLA3 family data sheet
Description
The CoolRunner™ XPLA3 XCR3032XL device is a 3.3V,
32-macrocell CPLD targeted at power sensitive designs
that require leading edge programmable logic solutions. A
total of two function blocks provide 750 usable gates.
Pin-to-pin propagation delays are as fast as 4.5 ns with a
maximum system frequency of 213 MHz.
TotalCMOS Design Technique for Fast
Zero Power
CoolRunner XPLA3 CPLDs offer a TotalCMOS solution,
both in process technology and design technique. Xilinx®
CPLDs employ a cascade of CMOS gates to implement its
sum of products instead of the traditional sense amp
approach. This CMOS gate implementation allows Xilinx to
offer CPLDs that are both high performance and low power,
breaking the paradigm that to have low power, one must
have low performance. Refer to
and
show-
ing the I
CC
vs. Frequency of the XCR3032XL TotalCMOS
CPLD (data taken with two resetable up/down, 16-bit
counters at 3.3V, 25° C).
20
Typical I
CC
(mA)
15
10
5
0
0
20
40
60
80
100
120
140
160
180
200
Frequency (MHz)
DS023_01_080101
Figure 1:
I
CC
vs. Frequency at V
CC
= 3.3V, 25°C
Table 1:
I
CC
vs. Frequency
(V
CC
= 3.3V, 25°C)
Frequency (MHz)
Typical I
CC
(mA)
0
0.017
1
0.13
5
0.54
10
1.06
20
2.09
50
5.2
100
10.26
200
20.3
© 2000–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS023 (v2.2) September 15, 2008
Product Specification
1