Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL V
CC
Clamping
R
Table 4:
Supported Sources for Spartan/XL Inputs
Spartan
Inputs
5V,
TTL
√
√
√
√
√
5V,
CMOS
Unreli-
able
Data
Spartan-XL
Inputs
3.3V
CMOS
√
√
√
√
(default
mode)
Source
Any device, V
CC
= 3.3V,
CMOS outputs
Spartan family, V
CC
= 5V,
TTL outputs
Any device, V
CC
= 5V,
TTL outputs (V
OH
≤
3.7V)
Any device, V
CC
= 5V,
CMOS outputs
Spartan-XL FPGAs have an optional clamping diode con-
nected from each I/O to V
CC
. When enabled they clamp
ringing transients back to the 3.3V supply rail. This clamping
action is required in 3.3V PCI applications. V
CC
clamping is
a global option affecting all I/O pins.
Spartan-XL devices are fully 5V TTL I/O compatible if V
CC
clamping is not enabled. With V
CC
clamping enabled, the
Spartan-XL devices will begin to clamp input voltages to
one diode voltage drop above V
CC
. If enabled, TTL I/O com-
patibility is maintained but full 5V I/O tolerance is sacrificed.
The user may select either 5V tolerance (default) or 3.3V
PCI compatibility. In both cases negative voltage is clamped
to one diode voltage drop below ground.
Spartan-XL devices are compatible with TTL, LVTTL, PCI
3V, PCI 5V and LVCMOS signalling. The various standards
are illustrated in
Table 5.
Table 5:
I/O Standards Supported by Spartan-XL FPGAs
Signaling
Standard
TTL
LVTTL
PCI5V
PCI3V
LVCMOS 3V
VCC
Clamping
Not allowed
OK
Not allowed
Required
OK
Output
Drive
12/24 mA
12/24 mA
24 mA
12 mA
12/24 mA
V
IH MAX
5.5
3.6
5.5
3.6
3.6
V
IH MIN
2.0
2.0
2.0
50% of V
CC
50% of V
CC
V
IL MAX
0.8
0.8
0.8
30% of V
CC
30% of V
CC
V
OH MIN
2.4
2.4
2.4
90% of V
CC
90% of V
CC
V
OL MAX
0.4
0.4
0.4
10% of V
CC
10% of V
CC
Additional Fast Capture Input Latch (Spartan-XL only)
The Spartan-XL IOB has an additional optional latch on the
input. This latch is clocked by the clock used for the output
flip-flop rather than the input clock. Therefore, two different
clocks can be used to clock the two input storage elements.
This additional latch allows the fast capture of input data,
which is then synchronized to the internal clock by the IOB
flip-flop or latch.
To place the Fast Capture latch in a design, use one of the
special library symbols, ILFFX or ILFLX. ILFFX is a trans-
parent-Low Fast Capture latch followed by an active High
input flip-flop. ILFLX is a transparent Low Fast Capture latch
followed by a transparent High input latch. Any of the clock
inputs can be inverted before driving the library element,
and the inverter is absorbed into the IOB.
Table 6:
Output Flip-Flop Functionality
Mode
Power-Up
or GSR
Flip-Flop
Clock
X
X
X
0
Legend:
X
SR
0*
1*
Z
Don’t care
Rising edge (clock not inverted).
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
3-state
Clock
Enable
X
0
1*
X
X
T
0*
0*
0*
1
0*
D
X
X
D
X
X
Q
SR
Q
D
Z
Q
IOB Output Signal Path
Output signals can be optionally inverted within the IOB,
and can pass directly to the output buffer or be stored in an
edge-triggered flip-flop and then to the output buffer. The
functionality of this flip-flop is shown in
Table 6.
8
1-800-255-7778
DS060 (v1.6) September 19, 2001
Product Specification
XILINX [ XILINX, INC ]
