YSS920B
Microprocessor interface format
Reading/writing of the internal control register is performed through the 4-line serial interface as shown
below:
1) When /CS is used only by one device
/CS
SCK
Don't Care A0 A1 A2 A3 A4 A5 A6 R/W D0 D1 D2 D3 D4 D5 D6 D7 Don't Care
SI
write
R/W = L
High impedance
SO
Don't Care A0 A1 A2 A3 A4 A5 A6 R/W
Don't Care
Don't Care
SI
read
R/W = H
High impedance
High
impedance
D0 D1 D2 D3 D4 D5 D6 D7
SO
SO is set to output mode only when all of the following conditions are met:
・ When /CS=L
・ When reading a valid address setting
・ During the output timing of data (8-bit).
In all other cases, it is set to High-Z, so that SO, SI, and SCK can be shared with devices having similar
interfaces. When multiple YSS920Bs are used, /CS can also be shared by specifying CHIP ADR register
CA3-0. See the next Section “ 2) “.
If the general-purpose input/output pin (IOPORT19-0) is used as an input pin (IPORT), then the IOPORT
(IPORT) value during the period of “R/W” shown above will be read through SO.
If it is used as an output pin (OPORT), then the IOPORT (OPORT) output will be switched over at the time
of SCK rising edge on “D7” shown above.
[Note] Set /CS to H during initial clear (/IC=L).
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YAMAHA [ YAMAHA CORPORATION ]
