SFSL5.5MDB 参数 Datasheet PDF下载

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3.2

Sleep Mechanism

Three signals are dedicated for Sleep wakeup mechanism

3.2.1

nSleep

Sleep control input from the host. This pin is high for normal operation, and low for Sleep Mode. When

not in use, this pin should be pulled Up.

3.2.2

Wake

Local wakeup input. Negative or positive edge wakes up the device. When not in use, this pin should be

pulled Up or Down.

3.2.3

INH

Inhibit output for enabling the host (or an external voltage regulator powering the host. This output is

LOW when in Sleep Mode, and HIGH in normal operation and after a wakeup event.

3.3

Line interface

Whenever a dual channel F0/F1 is required, the line interface is described in figure 3.2. It requires

addition analog switch such as FSA157 and two transistors for Tx and Rx drivers.

Ceramic

Filter F0

TxOn

MF0nF1

Data In

Tx.

Modulator

DTxO

RxOn

Tx.

Driver

DC Line

Data Out

Rx.

Demodulator

RxP

RxN

Rx.

Buffer

Ceramic

Filter F1

Figure 3.2 – DC - line interface block diagram

The line interface signals are:

3.3.1

DTxO

Modulated transmit signal output

3.3.2

TxOn

High when the device is transmitting

3.3.3

MF0nF1

Output signal indicates the selected channel. F0=”High”, F1= “Low”.

3.3.4

RxP

Comparator’s positive pin input signal. It swings around RxN.

3.3.5

RxN

Comparator’s negative pin input signal. Its value should be about Vcc/2.

@ 2007 Yamar Electronics Ltd.

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DS-SIG40 R1.8