eZ80F91 ASSP
Product Specification
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Architectural Overview
Zilog’s eZ80F91 device is a member of Zilog’s family of eZ80Acclaim! Flash Applica-
tion-Specific Standard Products (ASSPs). The eZ80F91 MCU is a high-speed ASSP with
a maximum clock speed of 50MHz and single-cycle instruction fetch. It operates in Z80-
compatible addressing mode (64KB) or full 24-bit addressing mode (16MB). The rich
peripheral set of the eZ80F91 makes it suitable for a variety of applications, including
industrial control, embedded communication, and point-of-sale terminals.
Features
The features of eZ80F91 ASSP device include:
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Single-cycle instruction fetch, high-performance, pipelined eZ80 CPU core
10/100 BaseT ethernet media access controller with Media-Independent Interface
(MII)
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256 KB Flash memory
16 KB SRAM (8KB user and 8 KB Ethernet)
Low-power features including SLEEP Mode, HALT Mode, and selective peripheral
power-down control
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Two Universal Asynchronous Receiver/Transmitter (UART) with independent Baud
Rate Generators (BRG)
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Serial Peripheral Interface (SPI) with independent clock rate generator
I2C with independent clock rate generator
IrDA-compliant infrared encoder/decoder
Glueless external peripheral interface with 4 chip selects, individual wait state genera-
tors, an external WAIT input pin; supports Z80-, Intel-, and Motorola-style buses
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Fixed-priority vectored interrupts (both internal and external) and interrupt controller
Real-time clock with separate VDD pin for battery backup and selectable on-chip
32kHz oscillator or external 50/60Hz input
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Four 16-bit Counter/Timers with prescalers and direct input/output drive
Watchdog Timer with internal oscillator clocking option
32 bits of General-Purpose Input/Output (GPIO)
On-Chip Instrumentation (OCI™) and Zilog Debug Interfaces (ZDI)
IEEE 1149.1-compatible JTAG
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
ZILOG [ ZILOG, INC. ]
