eZ80F91 ASSP
Product Specification
49
GPIO Mode 7: Alternate Functions
The port pin is configured to pass control over to the alternate (secondary) functions
assigned to the pin. For example, the alternate mode function for PC5 is the DSR1 input
signal to UART1 and the alternate mode function for PB4 is the timer 3 input capture.
When GPIO Mode 7 is enabled, the pin output data and pin high-impedance control is
obtained from the alternate function's data output and high-impedance control, respec-
tively. The value in the Port x Data Register produces no effect on operation. Input signals
are sampled by the system clock before being passed to the alternate input function.
If the alternate function of a pin is an input and alternate function mode for that pin is not
enabled, the input is driven to a default non-asserted value. For example, in alternate mode
function, PC5 drives the DSR1 signal to UART1. As this signal is Low level true, the
DSR1 signal to UART1 is driven to 1 when PC5 is not in alternate mode function.
GPIO Mode 8: Level Sensitive Interrupt
The port pin is configured for level-sensitive interrupt mode. The value in the Port x Data
Register determines if a low or high-level causes an interrupt request. An interrupt request
is generated when the level at the pin is the same as the level stored in the Port x Data Reg-
ister. The port pin value is sampled by the system clock. The input pin must be held at the
selected interrupt level for a minimum of two system clock periods to initiate an interrupt.
The interrupt request remains active as long as this condition is maintained at the external
source. For example, if a port pin is configured as a low-level-sensitive interrupt, the inter-
rupt request will be asserted when the pin has been low for two system clocks and remains
active until the pin goes high.
Configuring a pin for Mode 8 requires a transition through Mode 9 (edge-triggered mode).
To avoid the possibility of an unwanted interrupt while transition through Mode 9, observe
the following brief procedure to select Mode 8 when starting from the default mode (Mode
2):
1. Disable interrupts.
2. Set Px_DR = 0 (low level interrupt) or 1 (high level interrupt).
3. Set Px_ALT2 = 1.
4. Set Px_ALT1 =1 (Mode 9).
5. Set Px_DDR = 0 (Mode 8).
6. Set Px_ALT0 = 1 (to clear possible Mode 9 interrupt).
7. Enable interrupts.
GPIO Mode 9: Edge-Triggered Interrupt
The port pin is configured for single edge-triggered interrupt mode. The value in the Port x
Data Register determines whether a positive or negative edge causes an interrupt request.
Writing 0 to the Port x Data Register bit sets the selected pin to generate an interrupt
PS027004-0613
P R E L I M I N A R Y
General-Purpose Input/Output
ZILOG [ ZILOG, INC. ]
