eZ80L92 MCU
Product Specification
124
output following a 7-clock High (1) period. Following the 3-clock Low pulse, is a 6-clock
High pulse to complete the full 16-clock data period. Data transmission is illustrated in
Figure 26.
16-clock
period
Baud Rate
Clock
Start Bit = 0
1.6 µs
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RxD
min. pulse
UART_RxD
16-clock
period
16-clock
period
16-clock
period
16-clock
period
8-clock
delay
Figure 26. Infrared Data Reception
Jitter
Due to the inherent sampling of the received IR_RXD signal by the BIt Rate Clock, some
jitter can be expected on the first bit in any sequence of data. However, all subsequent bits
in the received data stream are a fixed 16-clock periods wide.
Infrared Encoder/Decoder Signal Pins
The infrared encoder/decoder signal pins (IR_TXD and IR_RXD) are multiplexed with
General-Purpose I/O (GPIO) pins. These GPIO pins must be configured for alternate func-
tion operation for the infrared encoder/decoder to operate.
The remaining six UART0 pins (CTS0, DCD0, DSR0, DTR0, RTS0 and RI0) are not
required for use with the infrared encoder/decoder. The UART0 modem status interrupt
should be disabled to prevent unwanted interrupts from these pins. The GPIO pins corre-
sponding to these six unused UART0 pins can be used for inputs, outputs, or interrupt
sources. Recommended GPIO Port D control register settings are provided in Table 66.
Refer to the section covering the General-Purpose Input/Output, on page 39 for additional
information about setting the GPIO Port modes
PS013012-1004
P R E L I M I N A R Y
Infrared Encoder/Decoder
ZILOG [ ZILOG, INC. ]
