eZ80L92 MCU
Product Specification
139
Data Validity
The data on the SDA line must be stable during the High period of the clock. The High or
Low state of the data line can only change when the clock signal on the SCL line is Low as
illustrated in Figure 30.
A Signal
L Signal
Data Line
Stable
Data Valid
Change of
Data Allowed
Figure 30. I
2
C Clock and Data Relationship
START and STOP Conditions
Within the I
2
C bus protocol, unique situations arise which are defined as START and
STOP conditions. See Figure 31. A High-to-Low transition on the SDA line while SCL is
High indicates a START condition. A Low-to-High transition on the SDA line while SCL
is High defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to
be busy after the
START
condition. The bus is considered to be free a defined time after
the
STOP
condition.
SDA Signal
SCL Signal
S
START Condition
P
STOP Condition
Figure 31. START and STOP Conditions In I
2
C Protocol
PS013012-1004
PRELIMINARY
I
2
C Serial I/O Interface
ZILOG [ ZILOG, INC. ]
