ZiLOG’s Family of
Serial Communication Controllers
SCC
8-bit Features include:
• Dual full-duplex channels (Z80230/Z85C30/Z85230)
• Single full-duplex channel (Z85233)
• Ability to accommodate a crystal oscillator, baud
rate generator, and digital phase-locked loop on
each channel
• Processing speeds up to 5Mbps
• Multi-protocol format (async, monosync, bisync,
ZiLOG Sets the standards for SCCs
For over 20 years ZiLOG has set the standard for
Serial Communication Controllers. Based on the
industry acclaimed SCC core, ZiLOG offers a wide
variety of Serial Communication Controllers to meet
your application requirements.
SDLC/HDLC, SDLC/HDLC loop)
• Encodes in the follow modes: NRZI, FM0, FM1
and Manchester
• CRC-16 or CRC-CCITT error detection
• 4-byte Transmit FIFO/8-byte Receive FIFO
(Z80230/Z85230/Z85233)
• 1-byte transmit FIFO/3-byte receive FIFO (Z85C30)
Reduces the need for external logic
ZiLOG SCCs offer low power consumption, higher
performance, and superior noise immunity. The many
on-chip features offered in ZiLOG SCCs help dramatically
to reduce the need for external logic and code develop-
ment found in most of the competition.
16-bit Solutions
The standard and integrated universal serial controllers,
Z16C30 and the Z16C32 offer 16-bit performance, with
processing speeds up to 20 Mbps.
16-bit Features include:
• Single (Z16C32) and dual (Z16C30)
full-duplex channels
• Accommodates two baud rate generators
and one digital phase-locked loop
• Processing speeds up to 10Mbps (Z16C30)
and 20Mbps (Z16C32)
• Multi-protocol format (async, monosync,
slaved monosync, bisync, isochronous,
nine-bit, SDLC/HDLC, SDLC/HDLC loop)
(additional 16-bit features on back)
8-bit Solutions
The standard serial and integrated communications
controller, Z85C30, allows you to easily implement a fully
integrated solution for many networking applications.
The enhanced dual and mono SCCs, the Z80230, Z85230
and the Z85233, include many features that make pro-
gramming easy. These parts also reduce CPU overhead,
allowing the programmer to select packet handling
response and improve cycle access recovery time.
ZILOG [ ZILOG, INC. ]
