Z16C30
Product Specification
7
The 8-bit bus with separate address is selected by setting BCR bit 2 to 0 and, during the
BCR write, forcing AD15 to a 1 and forcing AD14–AD8 to 0.
The multiplexed bus is selected for the USC if there is an Address Strobe prior to or during
the transaction which writes the BCR. If no Address Strobe is present prior to or during
the transaction which writes the BCR, a nonmultiplexed bus is selected (see
Pin Functions
RESET Reset (input, active Low)—
This signal resets the device to a known state. The
first write to the USC after a reset accesses the BCR to select additional bus options for the
device.
AS Address Strobe (input, active Low)—
This signal is used in the multiplexed bus
modes to latch the address on the AD lines. The AS signal is not used in the nonmulti-
plexed bus modes and should be tied to V
DD
.
DS Data Strobe (input, active Low)—
This signal strobes data out of the device during a
read and may strobe an interrupt vector out of the device during an interrupt acknowledge
cycle. DS also strobes data into the device on the state of R/W.
RD Read Strobe (input, active Low)—
This signal strobes data out of the device during a
read and may strobe an interrupt vector out of the device during an interrupt acknowledge
cycle.
WR Write Strobe (input, active Low)—
This signal strobes data into the device during a
write.
R/W Read/Write (input)—
This signal determines the direction of data transfer for a read
or write cycle in conjunction with DS.
CS Chip Select (input, active Low)—
This signal selects the device for access and must
be asserted for read and write cycles, but is ignored during interrupt acknowledge and fly-
by DMA transfers. In the case of a multiplexed bus interface, CS is latched by the rising
edge of AS.
A/B Channel A/Channel B Select (input)—
This signal selects between the two channels
in the device. High selects channel A and Low selects channel B. This signal is sampled
and the result is latched during the BCR (Bus Configuration Register) write. It programs
the sense of the WAIT/RDY signal appropriate for different bus interfaces.
D/C Data/Control Select (input)—
This signal, when High, provides for direct access to
the RDR and TDR. In the case of a multiplexed bus interface, D/
C
High overrides the
address provided to the device.
SITACK Status Interrupt Acknowledge (input, active Low)—
This signal is a status sig-
nal that indicates that an interrupt acknowledge cycle is in progress. The device is capable
of returning an interrupt vector that may be encoded with the type of interrupt pending
during this acknowledge cycle. This signal is compatible with 680X0 family microproces-
sors.
DS007902-0708
PRELIMINARY
Pin Description
ZILOG [ ZILOG, INC. ]
