Zilog
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLERS
FEATURES
Part
Z80185
Z80195
s
s
s
s
ROM
(KB)
32 x 8
0
UART
Baud Rate
512 Kbps
512 Kbps
Speed
(MHz)
20, 33
20, 33
s
s
s
100-Pin QFP Package
s
5.0-Volt Operating Range
s
Low-Power Consumption
s
0°C to +70°C Temperature Range
Low-EMI Option
Bidirectional Centronics Interface (IEEE 1284)
Two 8-Bit Parallel I/O Ports
Enhanced Z8S180 MPU
Four Z80 CTC Channels
One Channel ESCC
™
Controller
GENERAL DESCRIPTION
The Z80185 and Z80195 are smart peripheral controller
devices designed for general data communications appli-
cations, and architected specifically to accommodate all
input and output (I/O) requirements for serial and parallel
connectivity. Combining a high-performance CPU core
with a variety of system and I/O resources, the Z80185/195
are useful in a broad range of applications. The Z80195 is
the ROMless version of the device.
The Z80185 and Z80195 feature an enhanced Z8S180
microprocessor linked with one enhanced channel of the
Z85230 ESCC
™
serial communications controller, and 25
bits of parallel I/O, allowing software code compatibility
with existing software code.
Seventeen lines can be configured as bidirectional
Centronics (IEEE 1284) controllers. When configured as a
1284 controller, an I/O line can operate in either the host or
peripheral role in compatible, nibble, byte or ECP mode. In
addition, the Z80185 includes 32 Kbytes of on-chip ROM.
These devices are well-suited for external modems using
a parallel interface, protocol translators, and cost-effective
WAN adapters. The Z80185/195 is ideal for handling all
laser printer I/O, as well as the main processor in cost-
effective printer applications.
Notes:
All Signals with a preceding front slash, "/", are active Low.
Power connections follow conventional descriptions below:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
DS971850301
1
ZILOG [ ZILOG, INC. ]
