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  • A8904SLBT图
  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • A8904SLBT 现货库存
  • 数量5580 
  • 厂家 
  • 封装 
  • 批号2024+ 
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  • 北京首天国际有限公司

     该会员已使用本站16年以上
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  • 数量5000 
  • 厂家ALLEGRO 
  • 封装SOP24 
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  • 北京力通科信电子有限公司

     该会员已使用本站10年以上
  • A8904SLBT
  • 数量30 
  • 厂家ALLEGR 
  • 封装SOP24 
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  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • A8904SLB
  • 数量15000 
  • 厂家ALLEGRO 
  • 封装 
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  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • A8904SLBTR-T
  • 数量8800 
  • 厂家ALLEGRO/雅丽高 
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  • 集好芯城

     该会员已使用本站13年以上
  • A8904SLB
  • 数量8558 
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  • 封装SOP24 
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  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • A8904SLBT
  • 数量5600 
  • 厂家ALLEGR 
  • 封装SOP-24 
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  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
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  • 数量9465 
  • 厂家√ 欧美㊣品 
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  • 深圳市昌和盛利电子有限公司

     该会员已使用本站11年以上
  • A8904SLBTR-T
  • 数量19014 
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  • 封装原装正品 
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  • 深圳市科庆电子有限公司

     该会员已使用本站16年以上
  • A8904SLBT-TR
  • 数量1292 
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  • 现货只售原厂原装可含13%税
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • A8904SLB
  • 数量4225 
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  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • A8904SLB
  • 数量5000 
  • 厂家10 
  • 封装ALLEGRO 
  • 批号2024+ 
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  • 北京顺科电子科技有限公司

     该会员已使用本站8年以上
  • A8904SLB
  • 数量5500 
  • 厂家ALLEGRO/雅丽高 
  • 封装SOP-24 
  • 批号21+ 
  • 进口品牌//国产品牌代理商18911556207
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • A8904SLB
  • 数量69359 
  • 厂家ALLEGRO 
  • 封装SOP24 
  • 批号2023+ 
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  • 深圳市欧昇科技有限公司

     该会员已使用本站10年以上
  • A8904SLBT
  • 数量9000 
  • 厂家ALLGERO 
  • 封装SOP-24 
  • 批号2021+ 
  • 优势价格.十年专营渠道.深圳原装现货
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • A8904SLB
  • 数量4500 
  • 厂家ALLEGRO 
  • 封装SOP24 
  • 批号23+ 
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  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • A8904SLB
  • 数量3200 
  • 厂家ALLEGRO 
  • 封装SOP 
  • 批号23+ 
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  • 绿盛电子(香港)有限公司

     该会员已使用本站12年以上
  • A8904SLBT
  • 数量26976 
  • 厂家ALLEGRO 
  • 封装SOP24 
  • 批号2018+ 
  • ★★代理原装现货,特价热卖!★★
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • A8904SLBTR-T
  • 数量7800 
  • 厂家 
  • 封装SOP 
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  • 假一罚十,原装进口正品现货供应
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
  • A8904SLB
  • 数量4500 
  • 厂家ALLEGRO 
  • 封装SOP24 
  • 批号23+ 
  • 全新原装现货特价销售!
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  • 深圳市赛尔通科技有限公司

     该会员已使用本站12年以上
  • A8904SLB
  • 数量12850 
  • 厂家ALLGERO 
  • 封装SOP 
  • 批号NEW 
  • 绝对进口原装现货,市场价格最低!!
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  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
  • A8904SLB
  • 数量5500 
  • 厂家ALLEGRO 
  • 封装SOP24 
  • 批号20+ 
  • 百分百原装正品 真实公司现货库存 本公司只做原装 可开13%增值税发票,支持样品,欢迎来电咨询!
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • A8904SLBT
  • 数量40367 
  • 厂家ALLEGRO 
  • 封装SOP24 
  • 批号2023+ 
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • A8904SLBT
  • 数量3200 
  • 厂家ALLEGR 
  • 封装SOP 
  • 批号23+ 
  • 全新原装公司现货库存!
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  • 深圳市瑞天芯科技有限公司

     该会员已使用本站7年以上
  • A8904SLBT
  • 数量20000 
  • 厂家ALLEGRO 
  • 封装SOP24 
  • 批号22+ 
  • 深圳现货库存,保证原装正品
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  • 15973558688 QQ:1940213521
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  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • A8904SLBT
  • 数量8560 
  • 厂家ALLEGRO 
  • 封装SOP24 
  • 批号24+ 
  • ★★专业IC现货,诚信经营,市场最优价★★
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  • 上海振基实业有限公司

     该会员已使用本站13年以上
  • A8904SLBT
  • 数量998 
  • 厂家ALLEGRO 
  • 封装SMD 
  • 批号23+ 
  • 全新原装现货/另有约30万种现货,欢迎来电!
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  • 深圳市中利达电子科技有限公司

     该会员已使用本站11年以上
  • A8904SLBTR-T
  • 数量10000 
  • 厂家ALLEGRO/雅丽高 
  • 封装SOP24 
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  • 深圳市顺兴源微电子商行

     该会员已使用本站7年以上
  • A8904SLBT
  • 数量6890000 
  • 厂家ALLEGRO 
  • 封装SOP 
  • 批号16+ 
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  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • A8904SLBT
  • 数量5166 
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  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • A8904SLB
  • 数量3800 
  • 厂家Allegro 
  • 封装24-SOIC 
  • 批号24+ 
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  • 长荣电子

     该会员已使用本站14年以上
  • A8904SLB
  • 数量2500 
  • 厂家
  • 封装SOP 
  • 批号04+ 
  • 现货
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • A8904SLB
  • 数量98500 
  • 厂家ALLEG 
  • 封装SOP 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
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  • 深圳市创思克科技有限公司

     该会员已使用本站2年以上
  • A8904SLB
  • 数量7800 
  • 厂家ALLEGRO/雅丽高 
  • 封装SOP-24 
  • 批号20+ 
  • 全新原装原厂实力挺实单欢迎来撩
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  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • A8904SLBT
  • 数量30000 
  • 厂家ALLEGRO 
  • 封装SOP-24 
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  • 深圳市英德州科技有限公司

     该会员已使用本站2年以上
  • A8904SLBT
  • 数量30000 
  • 厂家ALLEGRO(美国埃戈罗) 
  • 封装 
  • 批号1年内 
  • 原厂渠道 正品保障 长期供应
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  • -0755-88604592 QQ:2355734291

产品型号A8904SLB的概述

芯片A8904SLB的概述 芯片A8904SLB是一款由高科技半导体应用公司开发的集成电路,主要用于电源管理和控制应用。它的设计旨在提供高效能、低功耗的解决方案,尤其适用于便携式设备和消费电子产品。A8904SLB能够处理多项复杂的电源管理任务,如电压调节、功率转换和电池充电等。 该芯片集成了多种功能,能够简化设计并降低系统成本。A8904SLB的灵活性和可配置性使得其能广泛应用于智能硬件、可穿戴设备和各类通信设备中。此外,它的高集成度设计使得整体电路板面积显著减小,便于在空间受限的环境中使用。 芯片A8904SLB的详细参数 A8904SLB具有丰富的技术参数,确保其在各种应用场合中的良好表现。以下是该芯片的一些关键规格参数: - 工作电压范围: 2.5V 至 5.5V - 输出电流: 最大可达 1A - 转换效率: 可高达 96% - 开关频率: 1MHz (可调) - 工作温度范...

产品型号A8904SLB的Datasheet PDF文件预览

8904  
3-PHASE BRUSHLESS DC MOTOR  
CONTROLLER/DRIVER WITH BACK-EMF SENSING  
A8904SLB (SOIC)  
The A8904SLB and A8904SLP are three-phase brushless dc motor  
controller/drivers designed for applications where accurate control of high-  
speed motors is required. The three half-bridge outputs are low on-resistance  
n-channel DMOS devices capable of driving up to 1.2 A. The A8904 provides  
complete, reliable, self-contained back-EMF sensing, motor startup and  
running algorithms. A programmable digital frequency-locked loop speed  
control circuit together with the linear current control circuitry provides  
precise motor speed regulation.  
A serial port allows the user to program various features and modes of  
operation, such as the speed control parameters, startup current limit, sleep  
mode, direction, and diagnostic modes.  
The A8904 is fabricated in Allegro’s BCD (Bipolar CMOS DMOS)  
process, an advanced mixed-signal technology that combines bipolar, analog  
and digital CMOS, and DMOS power devices. The A8904SLB is provided in  
a 24-lead wide-body SOIC batwing package. The A8904SLP is provided in a  
thin (<1.2 mm), 28-lead SSOP package with an exposed thermal pad. Each  
package type is available in a lead-free version (100% matte tin leadframe).  
Absolute Maximum Ratings  
Load Supply Voltage, VBB . . . . . . . . . . . . 15 V  
Features  
Output Current1, IOUT . . . . . . . . . . . . . . . . . . . . . ±1.4 A  
„ Pin-for-pin replacement for A8902CLBA  
PeakOutputCurrent(Brake)2,IOUT(BRK)  
Period2 for IOUT(BRK) to fall from  
. ±3.0 A  
„ Startup commutation circuitry  
±3.0 A to ±1.4 A . . . . . . . . . . . . . . . 800 ms  
Logic Supply Voltage, VDD . . . . . . . . . . . 7.0 V  
Logic Input Voltage Range, VIN  
„ Sensorless commutation circuitry  
„ Option of external sector data tachometer signal  
„ Option of external speed control  
„ Oscillator operation up to 20 MHz  
„ Programmable overcurrent limit  
„ Transconductance gain options: 500 mA/V or 250 mA/V  
„ Programmable watchdog timer  
(continuous) . . . . . . -0.3 V to VDD + 0.3 V  
(tw <30 ns) . . . . . . . -1.0 V to VDD + 1.0 V  
Package Power Dissipation, PD . . See Graph  
Operating Temperature, TA . . . -20°C to +85°C  
Junction Temperature3, TJ . . . . . . . . . +150°C  
Storage Temperature,TS . . . . -55°C to +150°C  
„ Directional control  
1Output current rating may be restricted to a value  
determined by system concerns and factors. These  
include: system duty cycle and timing, ambient  
temperature, and use of any heatsinking and/or forced  
cooling. For reliable operation, the specified maximum  
junction temperature should not be exceeded.  
2Peak output current is a transient condition that  
occurs during braking when the motor acts as a  
generator. The 3 A level is based on the maximum  
peak of a sine wave that is damped. The maximum  
period between the initial brake being applied and the  
current through the drivers falling to 1.4 A should not  
exceed 800 ms. See Braking section for more  
information.  
„ Serial Port Interface  
„ TTL-compatible inputs  
„ System diagnostics data out ported in real time  
„ Dynamic braking through serial port or external terminal  
Always order by complete part number:  
Part Number  
Package  
A8904SLB  
24-pin batwing SOIC  
3Fault conditions that produce excessive junction  
temperature will activate device thermal shutdown  
circuitry. These conditions can be tolerated, but should  
be avoided.  
A8904SLB-T  
A8904SLP  
A8904SLP-T  
24-pin batwing SOIC; Lead-free  
28-pin SSOP with Exposed Thermal Pad  
24-pin SSOP with Exposed Thermal Pad; Lead-free  
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
Functional Block Diagram  
(A8904SLB terminal numbers shown)  
115 Northeast Cutoff, Box 15036  
2
Worcester, Massachusetts 01615-0036 (508) 853-5000  
Copyright © 2003 Allegro MicroSystems, Inc.  
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
LB (SOIC) Package  
LP (HTSSOP) Package  
A8904SLP (HTSSOP)  
* Measured on “High-K” multi-layer PWB per JEDEC Standard  
JESD51-7.  
† Measured on typical two-sided PWB with power tabs (LB  
package) or thermal pad (LP package) connected to copper foil  
with an area of three square inches (1935 mm2). See Applica-  
tion Note 29501.5, Improving Batwing Power Dissipation, for  
additional information.  
www.allegromicro.com  
3
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5.0 V  
Limits  
Characteristic  
Symbol  
VDD  
Test Conditions  
Min.  
4.5  
Typ.  
Max.  
5.5  
10  
Units  
V
Logic Supply Voltage  
Logic Supply Current  
Operating  
Operating  
Sleep mode  
5.0  
7.5  
250  
3.6  
3.9  
IDD  
mA  
µA  
V
500  
Undervoltage Threshold  
UVLO  
Decreasing VDD  
Increasing VDD  
Operating  
V
Load Supply Voltage  
Load Supply Current  
VBB  
IBB  
4.0  
14  
V
Operating  
4.0  
20  
8.0  
30  
mA  
µA  
°C  
°C  
Sleep mode  
Thermal Shutdown  
TJ  
165  
20  
Thermal Shutdown Hysteresis  
Output Drivers  
TJ  
Output Leakage Current  
IDSX  
VBB = 14 V, VOUT = 14 V, sleep mode  
VBB = 14 V, VOUT = 0 V  
IOUT = 600 mA  
200  
-2.0  
1.0  
300  
-15  
1.4  
µA  
µA  
Total Output ON Resistance  
(source + sink + RS)  
rDS(on)  
Output Sustaining Voltage  
Clamp Diode Forward Voltage  
Control Logic  
VDS(sus)  
VF  
VBB = 14 V, IOUT = IOUT(MAX), L = 3 mH  
IF = 1.0 A  
14  
V
V
1.25  
1.5  
Logic Input Voltage  
VIN(0)  
VIN(1)  
IIN(0)  
SECTOR DATA, RESET, CLK,  
CHIP SELECT, OSC  
VIN = 0 V  
2.0  
0.8  
V
V
Logic Input Current  
-0.5  
±1.0  
2.0  
µA  
µA  
V
IIN(1)  
VIN = 5.0 V  
BRAKE Threshold  
VBRK  
IBRKL  
IBRK  
1.5  
1.75  
4.0  
20  
BRAKE Hysteresis Current  
BRAKE Current  
VBRK = 750 mV  
Brake set, D2 = 1, IBRK = 750 mV  
IOUT = 500 µA  
µA  
µA  
V
DATA Output Voltage  
VOUT(0)  
VOUT(1)  
ICST  
1.5  
IOUT = -500 µA  
Charging  
3.5  
-9.0  
V
CST Current  
-10  
500  
2.5  
1.0  
-10  
10  
-11  
µA  
µA  
V
Discharging, VCST = 2.5 V  
High  
CST Threshold  
Filter Current  
VCSTH  
VCSTL  
IFILTER  
2.25  
0.85  
-9.0  
9.0  
2.75  
1.15  
-11  
11  
Low  
V
Charging  
µA  
µA  
nA  
V
Discharging  
Leakage, VFILTER = 2.5 V  
±5.0  
2.13  
-22  
48  
Filter Threshold  
CD Current  
VFILTERTH  
ICD  
1.57  
-18  
32  
1.85  
-20  
40  
Charging  
µA  
µA  
V
(CD1 or CD2  
)
Discharging  
CD Current Matching  
CD Threshold  
ICD(DISCHRG)/ICD(CHRG)  
1.8  
2.25  
2.0  
2.5  
2.2  
2.75  
1.0  
VCDTH  
ICDIL  
CD Input Leakage  
µA  
Continued next page …  
115 Northeast Cutoff, Box 15036  
4
Worcester, Massachusetts 01615-0036 (508) 853-5000  
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
ELECTRICAL CHARACTERISTICS continued  
Limits  
Characteristic  
Symbol  
Test Conditions  
Charging, D26 = 0, D27 = 0  
Charging, D26 = 0, D27 =1  
Charging, D26 = 1 D27 = 0  
Charging, D26 = 1, D27 =1  
Min.  
-9.0  
-18  
-27  
-36  
0.22  
2.25  
20*  
20  
Typ.  
-10  
-20  
-30  
-40  
0.25  
2.5  
Max.  
-11  
-22  
-33  
-44  
0.28  
2.75  
Units  
µA  
CWD Current  
ICWD  
µA  
µA  
µA  
CWD Threshold Voltage  
VTL  
VTH  
V
V
Max. FLL Oscillator Frequency  
Oscillator High Duration  
Oscillator Low Duration  
fOSC  
MHz  
ns  
ton  
toff  
20  
ns  
Maximum Output Current  
IOUT(MAX)  
D3 = 0, D4 = 0, D28 = 0  
D3 = 0, D4 = 1, D28 = 0  
D3 = 1, D4 = 0, D28 = 0  
D3 = 1, D4 = 1, D28 = 0  
D3 = 0, D4 = 0, D28 = 1  
D3 = 0, D4 = 1, D28 = 1  
D3 = 1, D4 = 0, D28 = 1  
D3 = 1, D4 = 1, D28 = 1  
D28 = 1  
1.0  
0.9  
500  
1.2  
1.0  
600  
250  
600  
500  
300  
125  
250  
500  
10  
1.4  
1.1  
700  
A
A
mA  
mA  
mA  
mA  
mA  
mA  
mA/V  
mA/V  
kΩ  
mV  
500  
415  
700  
585  
Transconductance Gain  
gm  
210  
420  
5.0  
5.0  
290  
580  
13  
D28 = 0  
Centertap Resistors  
RCT  
Back-EMF Threshold with respect  
to  
20  
37  
VCTAP at FCOM transition  
-5.0  
-20  
-37  
mV  
Negative current is defined as coming out of (sourcing) the specified device terminal.  
* Operation at an oscillator frequency greater than the specified minimum value is possible but not waranteed.  
www.allegromicro.com  
5
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
Serial Port Timing Conditions  
CHIP SELECT  
E
A
B
D
CLOCK  
C
D
C
DATA  
Dwg. WP  
A. Minimum CHIP SELECT setup time before CLOCK rising edge ......... 100 ns  
B. Minimum CHIP SELECT hold time after CLOCK rising edge .............. 150 ns  
C. Minimum DATA setup time before CLOCK rising edge ....................... 150 ns  
D. Minimum DATA hold time after CLOCK rising edge ............................ 150 ns  
E. Minimum CLOCK low time before CHIP SELECT.................................. 50 ns  
F. Maximum CLOCK frequency .............................................................. 3.3 MHz  
G. Minimum CHIP SELECT high time ...................................................... 500 ns  
Note: the A8904 can be directly used in an existing A8902–A application, as the five most  
significant bits are reset to zero, which is the default condition for A8902–A operation. The  
only consideration when using the A8904 in an A8902-A application, is to ensure the  
minimum CHIP SELECT high time is at least 500 ns.  
115 Northeast Cutoff, Box 15036  
6
Worcester, Massachusetts 01615-0036 (508) 853-5000  
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
Terminal Functions  
A8904SLB A8904SLP  
Terminal Name  
LOAD SUPPLY  
CD2  
Function  
(SOIC)  
(HTSSOP)  
VBB; the 5 V or 12 V motor supply.  
1
2
15  
16  
One of two capacitors used to generate the ideal commutation points from  
the back-EMF zero crossing points.  
CWD  
Timing capacitor used by the watchdog circuit to blank out the back-EMF  
comparators during commutation transients, and to detect incorrect motor  
position.  
3
17  
CST  
NC  
Startup oscillator timing capacitor.  
No( internal) connection.  
4
18  
19  
20  
21  
OUTA  
Power amplifier A output to motor.  
No (internal) connection.  
5
NC  
GROUND  
POWER GROUND  
NC  
Power and logic ground and thermal heat sink.  
Power ground.  
6-7  
22*  
23  
24  
25  
26  
27  
No (internal) connection.  
OUTB  
Power amplifier B output to motor.  
Power amplifier C output to motor.  
Motor centertap connection for back-EMF detection circuitry.  
8
OUTC  
9
CENTERTAP  
10  
11  
Active low turns ON all three sink drivers shorting the motor windings to  
ground. External capacitor and resistor at BRAKE provide brake delay.  
The brake function can also be controlled via the serial port.  
BRAKE  
CRES  
External reservoir capacitor used to hold charge to drive the source drivers’  
gates. Also provides power for brake circuit.  
12  
28  
1*  
ANALOG GROUND  
FILTER  
Analog ground.  
Analog voltage input/output to control motor current. Also, compensation node  
for internal speed control loop.  
13  
14  
2
3
SECTOR DATA  
External tachometer input. Can use sector or index pulses from disk to  
provide precise motor speed feedback to internal frequency-locked loop.  
LOGIC SUPPLY  
OSCILLATOR  
DATA OUT  
VDD; the 5 V logic supply.  
15  
16  
17  
4
5
6
Clock input for the speed reference counter.  
Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in  
real time, controlled by 2-bit multiplexer via serial port.  
NC  
No (internal) connection.  
18-19  
7
GROUND  
Power and logic ground and thermal heat sink.  
Logic ground.  
DIGITAL GROUND  
8*  
9
When pulled low forces the chip into sleep mode; clears all serial port bits.  
No (internal) connection.  
20  
RESET  
NC  
10  
11  
12  
13  
14  
Strobe input (active low) for data word.  
Clock input for serial port.  
21  
22  
23  
24  
CHIP SELECT  
CLOCK  
DATA IN  
CD1  
Sequential data input for the serial port.  
One of two capacitors used to generate the ideal commutation points from  
the back-EMF zero crossing points.  
* For the A8904SLP, ground terminals 1, 8, and 22 must be connected together externally.  
www.allegromicro.com  
7
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
Functional Description  
sary, a transient voltage supply can be provided, by connecting  
an external Schottky power diode or pass FET in series, between  
the power source and the load supply (VBB). This FET or diode  
effectively isolates the low impedance path through the power  
source. A filter capacitor is also required to ‘hold up’ the  
rectified signal, and is connected between the load supply and  
ground.  
Overview of operation. Each electrical revolution  
contains six states that control the three half-bridge outputs.  
Optimized switching from state to state is achieved through the  
adaptive commutation circuitry. During any state, one output is  
high, one is low and the other is high impedance. The back-  
EMF at the high-impedance output is sensed and compared to  
the voltage of the centertap and when the two signals are  
equivalent, the FCOM signal toggles. A controlled delay is then  
introduced before the sequencer commutates into the next state.  
Back-EMF sensing motor startup and running  
algorithm. The A8904 provides a complete self-contained  
back-EMF sensing, startup and running commutation scheme. A  
state machine with six states, (shown in the tables below for  
both forward and reverse direction) controls the three half-  
bridge outputs. In each state, one output is high (sourcing  
current), one low (sinking current), and one is OFF (high  
impedance or ‘Z’). Motor back-EMF is sensed at the output that  
Linear current-mode control is employed to provide  
precision control of the motor speed while maintaining ex-  
tremely low electrical noise emissions. The speed control is  
realized through a frequency-locked loop that processes the  
sensed back-EMF signals from the stator phases to eventually  
produce a TACH signal. The TACH signal is then compared to  
the desired programmed speed, to produce an error. The error  
signal is then used to linearly control the current through the  
low-side DMOS power devices to obtain the correct speed.  
is OFF.  
Sequencer State  
(forward direction)  
OUTA  
High  
High  
Z
Low  
Low  
Z
OUTB  
Z
Low  
Low  
Z
OUTC  
Low  
Z
High  
High  
Z
Alternative control schemes can be introduced, giving the  
user maximum flexibility and optimization for each application.  
An external tachometer signal applied to the SECTOR DATA  
input, along with the internal speed reference can be used for  
high-precision speed control. As another alternative, the user can  
introduce external speed control by driving the FILTER terminal  
directly.  
1
2
3
4
5
6
High  
High  
Low  
Sequencer State  
Start-up routines are inherent in the solution to guarantee  
reliable start-up. During start-up, a YANK feature allows rapid  
transition to the nominal operating condition on the FILTER  
terminal. This feature is also available when the external speed  
control is used.  
(reverse direction)  
OUTA  
High  
Z
Low  
Low  
Z
OUTB  
Z
High  
High  
Z
OUTC  
Low  
Low  
Z
High  
High  
Z
1
6
5
4
3
2
Dynamic braking can be introduced by either the external  
BRAKE terminal or through the brake bit in the serial port.  
Low  
Low  
High  
A serial port allows the user to program various features and  
modes of operation, such as motor speed, internal or external  
speed control, internal or external speed reference, current limit,  
sleep mode, direction, charge current (for blanking pulse), motor  
poles, transconductance gain, and various diagnostic outputs.  
At start-up, the outputs are always enabled in state 1. The  
back-EMF is examined at the OFF output by comparing the  
output voltage to the motor centertap voltage at CENTERTAP.  
The motor will then either step forward, step backward or  
remain stationary (if in a null-torque position).  
Full device protection is incorporated, including program-  
mable overcurrent limit, thermal shutdown, and undervoltage  
shutdown on the logic supply.  
If the motor does not move during the initial start-up state,  
the outputs are commutated automatically by the start-up  
oscillator. When suitable back-EMF signals are detected, the  
start-up oscillator is overridden and the corresponding timing  
clock is generated, providing synchronous back-EMF commuta-  
tion. The start-up oscillator period is determined by  
tCST = (VCSTH - VCSTL) x CST / IST(charge)  
where CST is the start-up capacitor.  
Power outputs. The power outputs of the A8904 are n-  
channel DMOS transistors with a total source plus sink rDS(on) of  
typically 1 . An internal charge pump provides a voltage rail  
above the load supply for driving the high-side DMOS gates.  
Intrinsic ground clamp and flyback diodes provide protection  
when switching inductive loads. These diodes will also rectify  
the motor back-EMF during power-down conditions. If neces-  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
8
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
Functional Description (cont’d)  
If the motor moves, the back-EMF detection and direction  
circuit waits for the correct polarity of back-EMF zero crossing  
(output crossing through centertap). If the correct polarity of  
back-EMF is not detected, a watchdog circuit commutates the  
output until the correct back-EMF is detected. Correct back-  
EMF sensing is indicated by the FCOM signal, which toggles  
every time the back-EMF completes a zero crossing (see  
waveforms below). FCOM is available at the DATA OUT  
terminal.  
The typical delta voltage change during normal operation in  
the commutation capacitors (CD1 & CD2), will range between  
1.5 V and 2.0 V. The commutation capacitor values can be  
determined from:  
CDX = ICD x t / VCD  
where VCD = 1.5 V, ICD = 20 µA, and t = (60/rpm)/(#motor  
poles x 3), duration of each state.  
To avoid the capacitors charging to the supply rail, the value  
selected should provide adequate margin, taking into account the  
effects of capacitor tolerance, charging current, etc.  
Blanking and watchdog timing functions. The  
blanking and watchdog timing functions are derived from one  
timing capacitor CWD .  
True back-EMF zero crossings are used by the adaptive  
commutation delay circuit to advance the state sequencer  
(commutate) at the proper time to synchronously run the motor.  
See next section.  
During normal commutation, at the beginning of each new  
sequencer state, a blanking signal is created until the watchdog  
capacitor CWD is charged to the threshold VTL (see waveforms  
below). This blanking signal prohibits the back-EMF compara-  
tors from tripping due to the discharging of inductive energy and  
voltage settling transients during sequence state transitions. The  
duration of this blanking signal depends on the size of the CWD  
capacitor and the programmed charge current, ICWD (via D26-  
27). This blanking pulse also interrupts the commutation delay  
capacitors CD1 and CD2 from charging (see previous section).  
Adaptive commutation delay. The adaptive commuta-  
tion delay circuit uses the back-EMF zero-crossing indicator  
signal (FCOM) to determine an optimal commutation time for  
efficient synchronous switching of the output drivers. When the  
FCOM signal changes state, one of the delay capacitors (CD1 or  
CD2) is discharged at approximately twice the rate of the  
charging current. When the capacitor reaches the 2.5 V thresh-  
old, a commutation occurs. During this discharge period, the  
other delay capacitor is being charged in anticipation of the next  
FCOM state change. In addition, there is an interruption to the  
charging, which is set by the blanking duration (see waveform  
below, VCWD, and next section). This additional charging delay  
causes the commutation to occur at slightly less than 50% of the  
FCOM on or off duration, to compensate for delays caused by  
winding inductance.  
The ability to select the minimum charge current for CWD is  
particularly useful during start-up, where the duration of the  
diode recirculation current is highest. In applications where  
high motor speeds are experienced, the charge current can be  
increased so that the blanking period does not encroach signifi-  
cantly into the period of each sequencer state and does not cause  
www.allegromicro.com  
9
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
Functional Description (cont’d)  
unbalance in the commutation points.  
The duration of the watchdog-triggered commutation is  
determined by:  
It is recommended to select the value of CWD in the actual  
application circuit with the A8904 put into step mode. CST  
should be reselected (only for this test), to be between 4.7 µF  
and 10 µF, so that the motor comes to rest between steps and the  
maximum diode conduction time can be measured. The value of  
CWD can be determined as:  
CWD = ICWD x td / VTL  
where td = measured diode conduction, ICWD = charge current at  
start-up, and VTL = 250 mV.  
tWD = VTH x CWD / ICWD  
where ICWD = normal charge current.  
Speed control. The actual speed of the motor is mea-  
sured by either internally sensing the back-EMFs or by an  
external scheme via the SECTOR DATA terminal. A TACH  
signal is produced from these signals, which is then compared  
against the desired speed, which is programmed into a 14-bit  
counter (see diagram and waveforms below - assumes internal  
scheme used). The resulting error signal, ERROR, is then used  
to charge or discharge the FILTER terminal capacitor depending  
on whether the motor is running too slow or too fast. The  
FILTER terminal voltage is used to linearly drive the low-side  
MOSFETs to match the desired speed.  
V
TL  
V
CWD  
t
BLANK  
BLANK  
Each back-EMF signal detected causes the state of the  
FCOM signal to change. The number of FCOM transitions per  
mechanical revolution is equal to the number of poles times 3.  
For example, with a 4-pole motor (as shown on next page), the  
number of FCOM transitions will equal 12 per mechanical  
revolution. The number of poles are programmed via serial port  
bits D20 and D21. There are six electrical states per electrical  
revolution, therefore, for this example, there are 12 commuta-  
tions or two electrical revolutions per mechanical revolution.  
Dwg. WP-022  
Normal commutation  
V
TH  
V
TL  
V
CWD  
The TACH signal changes state once per mechanical  
revolution and as well as providing information on the actual  
motor speed is also used to trigger the REF counter which  
contains the information on the desired motor speed. Alterna-  
tively an external TACH signal can be used, an explanation of  
which is presented in the Sector Mode Section.  
t
BLANK  
BLANK  
t
WD  
Dwg. WP-021  
Watchdog-triggered commutation  
The duration of REF is set by programming the counter to  
count the desired number of OSCILLATOR cycles, according to  
the following:  
After the watchdog capacitor CWD charges to the VTL threshold,  
and if the correct polarity of back-EMF signal is detected, the  
back-EMF detection circuit discharges CWD to zero volts (see  
waveform above) and the circuit is ready to detect the next back-  
EMF zero crossing.  
total count = 60 x fOSC / desired motor speed (rpm)  
where the total count (number of oscillator cycles) is equal to the  
sum of the count numbers selected through bits D5 to D18 in the  
serial port and fOSC corresponds to the OSCILLATOR fre-  
quency.  
If the correct polarity of back-EMF is not detected between  
the blanking period, tBLANK, and the watchdog period, tWD, then  
the back-EMF detection circuit does not allow the watchdog  
capacitor CWD to be discharged and the watchdog circuit  
commutates the outputs to the next sequencer state (see wave-  
form above). This mode of operation continues until a suitable  
back-EMF signal is detected. This function is useful in prevent-  
ing excessive reverse rotation, and helps in resynchronising (or  
starting) with a moving spindle.  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
10  
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
Functional Description (cont’d)  
Speed error detection  
The FILTER voltage is then used to provide linear current  
control in the windings via the transconductance stage (see  
diagram next page). The output current is sensed through an  
internal sense resistor, RS. The voltage across the sense resistor  
is compared to the lowest of either one-tenth of the voltage at the  
FILTER terminal, minus the filter threshold voltage, or to the  
maximum current limit reference.  
Alternatively, external control of the FILTER terminal can  
be introduced by disabling the frequency-lock loop circuitry  
(D24 = 1).  
The transconductance function is defined as:  
IOUT = (VFILTER – VFILTERTH) / (10 x RS x G)  
where RS is nominally 200 m,  
VFILTERTH is approximately 1.85 V,  
G = 1, when D28 = 0 and gain = 500 mA/V or  
G = 2, when D28 = 1 and gain = 250 mA/V.  
Speed error signals  
The closed loop control response of the overall system is  
shaped via the filter components that are introduced at the  
FILTER terminal.  
A speed error signal is created by integrating the differences  
between the TACH and REF signal. If the TACH signal goes  
low before the REF signal then an ERROR FAST is produced  
and if the TACH signal goes low after the REF signal then an  
ERROR SLOW is produced. The error signal generated enables  
the appropriate current source (see diagram next page) to either  
charge or discharge the filter components on the FILTER  
terminal.  
Clamping the current to a level defined by the serial port  
(D3 & D4) provides output current limit protection. This feature  
is particularly useful where high transient currents are experi-  
enced, e.g., during start-up. Once normal running conditions are  
reached, the current limit can be appropriately reduced. Note  
that the current limit is scaled according to the gm value selected.  
www.allegromicro.com  
11  
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
Functional Description (cont’d)  
Speed and current control  
VFILTERTH, by the internal YANK command and the initial  
Sector mode. An external tachometer signal, such as  
sector or index pulses, can be used to create the TACH signal,  
rather than the internally generated once-around scheme. The  
external signal is applied to the SECTOR DATA terminal and  
the serial port bit (D19 = 1) must be programmed to enable this  
feature.  
output current will be set to the maximum selected current limit.  
This condition is maintained until the motor reaches the correct  
speed and the first ERROR FAST signal is produced which  
removes the YANK and allows linear current control.  
The YANK feature is also activated when an external speed  
control scheme is used (D24 = 1). To ensure the YANK is  
released at start-up by the internal speed control, it is important  
to ensure the speed reference is set at a lower speed than what  
the motor is designed to run at. Note that when the serial port is  
programmed to run initially, the default condition for the speed  
is set for the slowest condition so this will guarantee the YANK  
to be released. It is important when using external speed control  
that, as a minimum, the number of poles, speed control mode,  
and speed reference are programmed in the serial port.  
In applications where both internal and external TACH  
signals are used, it is important to only switch between modes  
when the SYNC signal on DATA OUT is low. This ensures the  
speed control information that is being processed during the  
transition, is not corrupted. SYNC is accessed through the  
DATA OUT multiplexer, which is controlled by D22 & D23.  
DATA OUT. The DATA OUT terminal is the output of a  
2-bit input multiplexer controlled by D22 & D23 of the serial  
port. Data available are TACH signal (internally or externally  
generated), SYNC signal, FCOM signal, and thermal shutdown  
(LOW = A8904 operating within thermal limits, HIGH =  
thermal shutdown has occurred).  
Forward/reverse. Directional control is managed  
through D25 in the serial port.  
Serial port. Control features and diagnostic data selection  
are communicated to the A8904 through the 29-bit serial port.  
See serial port timing diagrams on page 6. When CHIP SE-  
LECT is low, data is written to the serial port on the positive  
edge of the clock with the MSB (D28) fed in first. At the end of  
Speed loop initialization (YANK). To ensure rapid  
transition from start-up to the normal operating condition, the  
FILTER terminal is pulled up to the filter threshold voltage,  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
12  
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
Functional Description (cont’d)  
the write cycle, the CHIP SELECT goes high, the serial port is  
disabled and no more data can be transferred. In addition, the  
data written to the serial port is latched and becomes active.  
Bit number  
Count number  
D5  
D6  
16  
32  
If a word of less than 29 bits is sent, the unused most  
significant bits that are not programmed, are reset to zero. There  
are no compatibility issues when using the A8904 in an existing  
A8902-A application as the five MSBs are reset to zero, which  
is the default condition for A8902-A operation. The only  
consideration when using the A8904 in an A8902-A application  
is to ensure the minimum CHIP SELECT high time is at least  
500 ns.  
D7  
D8  
D9  
64  
128  
256  
512  
1,024  
2,048  
4,096  
8,192  
16,384  
32,768  
65,536  
131,072  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D0 - Sleep/Run Mode; LOW = Sleep, HIGH = Run. This  
bit allows the device to be powered down when not in use.  
D1 - Step Mode; LOW = Normal Operation, HIGH = Step  
Only. When in the step-only mode the back-EMF commutation  
circuitry is disabled and the start-up oscillator commutates the  
power outputs. This mode is intended for device and system  
testing.  
D19 - Speed control mode; LOW = internal, once-around  
speed signal, HIGH = external sector data.  
D20 and D21 - Programs the number of motor poles for the  
once-around FCOM counter.  
D2 - Brake; LOW = Run, HIGH = Brake.  
D3, D4, and D28 - The output current limit is set by D3 &  
D4; D28 sets the transconductance gain.  
D20  
D21  
Motor poles  
0
0
1
1
0
1
0
1
8
4
16  
12  
Current limit Transconductance  
D3 D4 D28  
(typical)  
gain  
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
1.2 A  
1.0 A  
500 mA/V  
500 mA/V  
500 mA/V  
500 mA/V  
250 mA/V  
250 mA/V  
250 mA/V  
250 mA/V  
D22 and D23 - Controls the multiplexer for DATA OUT.  
See DATA OUT Section for status definitions.  
600 mA  
250 mA  
600 mA  
500 mA  
300 mA  
125 mA  
D22 D23  
DATA OUT  
0
0
1
1
0
1
0
1
TACH (once around or sector) signal  
Thermal shutdown  
SYNC signal  
FCOM signal  
D5 to D18 - 14-bit word, active low. Programs the count  
number to produce the corresponding REF signal, which  
indicates the desired motor speed.  
D24 - Speed Reference. LOW = Internal, using back-EMF  
technique, HIGH = External (internal control disabled).  
D25 - Direction. LOW = Forward, HIGH = Reverse.  
D26 and D27 - Programs the charging current for the  
watchdog capacitor. This function is used for adjusting the  
blanking duration and also the watchdog commutation period.  
D26 D27  
Watchdog charge current (typical)  
0
0
1
1
0
1
0
1
-10 µA  
-20 µA  
-30 µA  
-40 µA  
www.allegromicro.com  
13  
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
Functional Description (cont’d)  
head to retract before activating the spindle motor brake. The  
brake delay can be simply implemented by using an external RC  
and diode to control the brake terminal.  
D28 - Programs the transconductance gain. LOW = 500 mA/V,  
HIGH = 250 mA/V.  
Reset. When the RESET terminal is pulled low, all the  
serial port bits are reset to LOW and the part operates in sleep  
mode.  
Undervoltage lockout, VDD. When an undervoltage  
condition occurs, all the serial port bits are reset to LOW and the  
part operates in sleep mode.  
V
– V  
BRAKE  
ACTIVATED  
FAULT  
D
BRAKE  
FAULT  
C
B
V
R
BRK  
B
t
BRK  
Dwg. OP-004  
Charge pump. The charge pump is required to provide a  
voltage rail above the load supply for driving the high-side  
DMOS gates. In addition the charge pump supply capacitor,  
CRES, also powers the brake control circuit during power-down  
conditions. CRES should be 220 nF.  
Braking. A dynamic braking feature of the A8904 shorts  
the three motor windings to ground. This is accomplished by  
turning the three source drivers OFF and the three sink drivers  
ON. Activation of the brake can be implemented through the  
BRAKE input or through the D2 bit in the serial port.  
During braking, the motor is effectively acting as three sine-  
wave voltage generators, 120° out of phase, where the voltage  
developed by each of the windings is proportional to the motor  
speed and constant. The current through any sink driver is  
simply the generated voltage divided by the center tap to OUT  
resistance plus the sink driver resistance. As the motor tends to  
slow during the braking process, both the generated voltage and  
the corresponding current decreases.  
When selecting a motor to use where braking will be  
applied, it is important to characterize the application to ensure  
that when braking is applied, the peak current in the sink drivers  
does not exceed 3A and the period from the peak current to the  
maximum current limit of the drivers does not exceed 800 ms.  
Another consideration is the thermals of the solution, where  
repeated spin-up followed by brake cycles could cause excessive  
junction temperatures.  
The brake delay can be set using the equation:  
tBRK = –RBCB x ln (VBRK / [VFAULT – VD]).  
Once the brake is activated, the three sink drivers will  
remain active until the supply rails fall below the operating  
range. It is recommended that the part is reset before restarting.  
Centertap. It is recommended that the centertap connec-  
tion of the motor be connected to the CENTERTAP terminal. If  
the centertap of the motor is not connected to the CENTERTAP  
terminal, the A8904 internally emulates the centertap voltage of  
the motor through a series of 10 kresistors connected between  
each output and CENTERTAP. This technique does not provide  
ideal commutation points.  
External component selection. All capacitors should  
be rated to at least 25 V and the dielectric should be X7R, apart  
from the start-up capacitor CST, which can be Z5U dielectric or  
equivalent and the input capacitor Cfilter, which should be an  
electrolytic type of value greater than 100 µF, 35 V, Iripple > 100  
mA. If the solution experiences ambient temperatures of greater  
than 70°C then Cfilter should be rated for 105°C.  
All resistors are at least 1/8 W and have a tolerance of ±5%.  
In noise-sensitive systems where electromagnetic interfer-  
ence is an issue, or to stabilize the current waveforms with  
certain motors, it may be necessary to add RC snubbers across  
the motor windings as shown in the application circuit on the  
next page. The A8904 solution should be relatively noise  
immune from the effects of switching voltage spikes etc. if the  
correct watchdog capacitor has been selected for optimum  
blanking and good layout practices are implemented.  
The supply voltage for the brake circuit is derived from the  
charge pump supply capacitor, CRES. With CRES chosen to be  
220 nF, the brake circuit will function for at least 100 ms after a  
power failure.  
In certain applications such as disk drives, it is desirable to  
include a brake delay to allow sensitive circuitry such as the disk  
At the range of operating frequencies that the current pulses  
are drawn out of the load supply, it is the capacitance reactance  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
14  
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
as opposed to the ESR that dominates the overall impedance of  
the input filter, Cfilter. Therefore, it is possible to reduce con-  
ducted electromagnetic emissions further, by simply increasing  
the value of Cfilter. In extremely sensitive systems, it may be  
necessary to introduce a differential mode inductor in series with  
the load supply line.  
inductive loops and radiated emissions. The ground plane  
should cover the area beneath the A8904 and extend beyond the  
outline to form a plane around all the external components. The  
exposed thermal pad of the HTSSOP part should be connected  
to the ground plane.  
Filter components, especially Cfilter, timing, and delay  
capacitors should be positioned as close as possible to the device  
terminals. It is also imperative that the traces to the serial port  
and oscillator are as short and as wide as possible to reduce stray  
inductance and prevent potential data corruption. In addition,  
these traces should be positioned well away from any noisy  
signals.  
Layout considerations. The HTSSOP part (A8904SLP)  
has three separate ground connections, analog, digital, and  
power that must be connected together externally. A ground  
plane should be used to provide heat sinking for the power  
switches and the reduction of potential noise pick-up through  
Typical application  
(A8904SLB)  
www.allegromicro.com  
15  
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
A8904SLB (SOIC)  
24  
13  
0.01  
0.00  
0.419  
0.394  
0.2992  
0.2914  
0.050  
0.016  
0.020  
0.013  
1
2
3
0.050  
BSC  
0.6141  
0.5985  
0° TO 8°  
Dimensions in Inches  
(for reference only)  
NOTE 1  
NOTE 3  
0.0926  
0.1043  
Dwg. MA-008-25A in  
0.0040 MIN.  
24  
0.32  
0.23  
10.65  
10.00  
7.60  
7.40  
1.27  
0.40  
0.51  
0.33  
1
2
1.27  
BSC  
3
15.60  
15.20  
TO 8°  
Dimensions in Millimeters  
(controlling dimensions)  
NOTE 1  
NOTE 3  
2.65  
2.35  
Dwg. MA-008-25A mm  
0.10 MIN.  
NOTES: 1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.  
2. Lead spacing tolerance is non-cumulative.  
3. Exact body and lead configuration at vendor’s option within limits shown.  
4. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number  
for tape and reel.  
115 Northeast Cutoff, Box 15036  
16  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
A8904SLP (HTSSOP)  
Dimensions in Inches  
(for reference only)  
Dimensions in Millimeters  
(controlling dimensions)  
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.  
2. Lead spacing tolerance is non-cumulative.  
3. Supplied in standard sticks/tubes of 49 devices or add “TR” to part number for tape and reel.  
www.allegromicro.com  
17  
8904  
3-PHASE BRUSHLESS DC  
MOTOR CONTROLLER/DRIVER  
The products described here are manufactured under one or more  
U.S. patents or U.S. patents pending.  
Allegro MicroSystems, Inc. reserves the right to make, from time to  
time, such departures from the detail specifications as may be required  
to permit improvements in the performance, reliability, or  
manufacturability of its products. Before placing an order, the user is  
cautioned to verify that the information being relied upon is current.  
Allegro products are not authorized for use as critical components  
in life-support devices or systems without express written approval.  
The information included herein is believed to be accurate and  
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-  
bility for its use; nor for any infringement of patents or other rights of  
third parties which may result from its use.  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
18  
配单直通车
A8904SLB产品参数
型号:A8904SLB
是否Rohs认证:不符合
生命周期:Obsolete
IHS 制造商:ALLEGRO MICROSYSTEMS LLC
零件包装代码:SOIC
包装说明:SOP, SOP24,.4
针数:24
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.85
Is Samacsys:N
模拟集成电路 - 其他类型:BRUSHLESS DC MOTOR CONTROLLER
JESD-30 代码:R-PDSO-G24
JESD-609代码:e0
长度:15.4 mm
功能数量:1
端子数量:24
最高工作温度:85 °C
最低工作温度:-20 °C
最大输出电流:1.4 A
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP24,.4
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240
电源:5,4/14 V
认证状态:Not Qualified
座面最大高度:2.65 mm
子类别:Motion Control Electronics
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V
表面贴装:YES
技术:BCDMOS
温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:30
宽度:7.5 mm
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