AD2S81AJD应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

Variable Resolution, Monolithic

Resolver-to-Digital Converters

a

AD2S81A/AD2S82A

AD2S82A FUNCTIONAL BLOCK DIAGRAM

FEATURES

Monolithic (BiMOS ll) Tracking R/D Converter

Ratiometric Conversion

INTEGRATOR

I/P

DEMOD DEMOD

I/P O/P

Low Power Consumption: 300 mW Typ

Dynamic Performance Set by User

Velocity Output

AD2S82A

PHASE

SENSITIVE

DETECTOR

INTEGRATOR

O/P

SIN I/P

SIGNAL

GND

COS I/P

ANALOG

GND

A1

A2

SEGMENT

SWITCHING

ESD Class 2 Protection (2,000 V Min)

R-2R

DAC

AC ERROR

O/P

A3

AD2S81A

28-Lead DIP Package

Low Cost

RIPPLE

CLK

VCO I/P

INHIBIT

VCO O/P

VCO DATA

TRANSFER

LOGIC

16-BIT

UP/DOWN COUNTER

OUTPUT DATA LATCH

16 DATA BITS

+12V

–12V

AD2S82A

44-Lead PLCC Package

10-, 12-, 14- and 16-Bit Resolution Set by User

High Max Tracking Rate 1040 RPS (10 Bits)

VCO Output (Inter LSB Output)

Data Complement Facility

COMP

+5V

DATA

LOAD

DIGITAL

GND

BUSY DIR

SC2

SC1 ENABLE

BYTE

SELECT

Industrial Temperature Range

An analog signal proportional to velocity is also available and

can be used to replace a tachogenerator.

APPLICATIONS

DC Brushless and AC Motor Control

Process Control

Numerical Control of Machine Tools

Robotics

Axis Control

PRODUCT HIGHLIGHTS

Monolithic. A one-chip solution reduces the package size re-

quired and increases the reliability.

Resolution Set by User. Two control pins are used to select

the resolution of the AD2S82A to be 10, 12, 14 or 16 bits al-

lowing the user to use the AD2S82A with the optimum resolu-

tion for each application.

GENERAL DESCRIPTION

The AD2S82A is a monolithic 10-, 12-, 14- or 16-bit tracking

resolver-to-digital converter contained in a 44-lead J leaded

PLCC package. Two extra functions are provided in the new

surface mount package–COMPLEMENT and VCO output.

Ratiometric Tracking Conversion. Conversion technique

provides continuous output position data without conversion

delay and is insensitive to absolute signal levels. It also provides

good noise immunity and tolerance to harmonic distortion on

the reference and input signals.

The AD2S81A is a monolithic 12-bit fixed resolution tracking

resolver-to-digital converter packaged in a 28-lead DIP.

The converters allow users to select their own dynamic performance

with external components. This allows the users great flexibility in

defining the converter that best suits their system requirements.

The AD2S82A allows users to select the resolution to be 10, 12,

14 or 16 bits and to track resolver signals rotating at up to 1040

revs per second (62,400 rpm) when set to 10-bit resolution.

Dynamic Performance Set by the User. By selecting exter-

nal resistor and capacitor values the user can determine band-

width, maximum tracking rate and velocity scaling of the

converter to match the system requirements. The external com-

ponents required are all low cost, preferred value resistors and

capacitors, and the component values are easy to select using

the simple instructions given.

The AD2S81A and AD2S82A convert resolver format input

signals into a parallel natural binary digital word using a ratio-

metric tracking conversion method. This ensures high-noise

immunity and tolerance of lead length when the converter is

remote from the resolver.

Velocity Output. An analog signal proportional to velocity is

available and is linear to typically one percent. This can be used

in place of a velocity transducer in many applications to provide

loop stabilization in servo controls and velocity feedback data.

The output word is in a three-state digital logic form available in

two bytes on the 16 output data lines for the AD2S82A and on

eight output data lines for the AD2S81A. BYTE SELECT,

ENABLE and INHIBIT pins ensure easy data transfer to 8- and

16-bit data buses, and outputs are provided to allow for cycle or

pitch counting in external counters.

Low Power Consumption. Typically only 300 mW.

MODELS AVAILABLE

Information on the models available is given in the Ordering

Guide.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(@ T = +25؇C, unless otherwise noted)

AD2S81A/AD2S82A–SPECIFICATIONS

A

AD2S81A

AD2S82A

Typ

Parameter

Conditions

Min

Typ

Max

Min

Max

Units

SIGNAL INPUTS

Frequency

400

1.8

20,000

2.2

50

20,000

2.2

Hz

V rms

nA

MΩ

V pk

Voltage Level

2.0

60

1.8

2.0

60

Input Bias Current

Input Impedance

Maximum Voltage

150

1.0

±8

REFERENCE INPUT

Frequency

400

1.0

20,000

8.0

150

50

20,000

8.0

150

Hz

Voltage Level

1.0

V pk

nA

Input Bias Current

Input Impedance

60

1.0

MΩ

CONTROL DYNAMICS

Repeatability

Allowable Phase Shift

Tracking Rate

1

LSB

Degrees

rps

(Signals to Reference)

10 Bits

–10

+10

–10

+10

1040

260

65

12 Bits

260

rps

14 Bits

16 Bits

User Selectable

rps

16.25

Bandwidth¹

ACCURACY

Angular Accuracy

H

؎22 + 1 LSB arc min

J

؎30 + 1 LSB

؎8 + 1 LSB

؎4 + 1 LSB

؎2 + 1 LSB

arc min

K

L

Monotonicity

Guaranteed Monotonic

Missing Codes (16-Bit Resolution) J, K

L

4

1

Codes

Code

VELOCITY SIGNAL

Linearity

Over Full Range

±1

؎3

±2

6

±1

؎3

±2

6

% FSD

mV

µV/°C

% FSD

V

Reversion Error

DC Zero Offset²

DC Zero Offset Tempco

Gain Scaling Accuracy

Output Voltage

Dynamic Ripple

Output Load

–22

؎10

±10.5

1.5

؎10

±10.5

1.5

1 mA Load

Mean Value

±8

±9

±8

±9

% rms O/P

kΩ

1.0

INPUT/OUTPUT PROTECTION

Analog Inputs

Analog Outputs

Overvoltage Protection

Short Circuit O/P Protection

±8

V

mA

±5.6

±10.4

±5.6

±10.4

DIGITAL POSITION

Resolution

Output Format

Load

10, 12, 14 and 16

Bidirectional Natural Binary

3

LSTTL

ns

INHIBIT³

Sense

Logic LO to Inhibit

Time to Stable Data

600

ENABLE³

Logic LO Enables Position

Output. Logic HI Outputs in

High Impedance State

ENABLE/Disable Time

35

60

110

140

35

60

110

140

ns

BYTE SELECT³

Sense

Logic HI

MS Byte DB1–DB8,

(LS Byte DB9–DB16)⁴

LS Byte DB1–DB8,

(LS Byte DB9–DB16)⁴

Logic LO

Time to Data Available

SHORT CYCLE INPUTS^{4, 5}

Internally Pulled High

(100 kΩ) to +V_S

SC1

SC2

0

1

0

1

0

1

10 Bit

12 Bit

14 Bit

16 Bit

DATA LOAD^{4, 5}

Sense

Internally Pulled High (100 kΩ)

to +V_S;Logic LO Allows

150

300

ns

Data to Be Loaded into the

Counters from the Data Lines

–2–

REV. B

AD2S81A/AD2S82A

AD2S81A

Typ

AD2S82A

Parameter

Conditions

Min

200

Max

Min

200

Typ

Max

Units

COMPLEMENT^{4, 5}

Internally Pulled High (100 kΩ) to

+V_S; Logic LO to Activate; No

Connect for Normal Operation

BUSY³

Sense

Width

Load

Logic HI When Position O/P Changing

Use Additional Pull-Up

600

1

600

1

ns

LSTTL

DIRECTION³

Sense

Logic HI Counting Up

Logic LO Counting Down

Max Load

3

LSTTL

RIPPLE CLOCK³

Sense

Logic HI, All 1s to All 0s

All 0s to All 1s

Width

Reset

Load

Dependent On Input Velocity

Before Next Busy

300

2.0

300

2.0

3

LSTTL

V

DIGITAL INPUTS

High Voltage, V_IH

INHIBIT, ENABLE

DB1–DB16, Byte Select

±V_S= ±10.8 V, V_L= 5.0 V

INHIBIT, ENABLE

DB1–DB16, Byte Select

±V_S= ±13.2 V, V_L= 5.0 V

Low Voltage, V_IL

0.8

V

DIGITAL INPUTS

High Current, I_IH

INHIBIT, ENABLE

DB1–DB16

±V_S= ±13.2 V, V_L= 5.5 V

INHIBIT, ENABLE

DB1–DB16, Byte Select

±V_S= ±13.2 V, V_L= 5.5 V

؎100

µA

Low Current, I_IL

DIGITAL INPUTS

Low Voltage, V_IL

ENABLE = HI

1.0

V

SC1, SC2, Data Load

±V_S= ±12.0 V, V_L= 5.0 V

ENABLE = HI

Low Current, I_IL

–400

µA

SC1, SC2, Data Load

±V_S= ±12.0 V, V_L= 5.0 V

DIGITAL OUTPUTS

High Voltage, V_OH

DB1–DB16; RIPPLE CLK, DIR

±V_S= ±12.0 V, V_L= 4.5 V

I_OH= 100 µA

DB1–DB16, RIPPLE CLK, DIR

±V_S= ±12.0 V, V_L= 5.5 V

I_OL= 1.2 mA

2.4

V

Low Voltage, V_OL

0.4

THREE-STATE LEAKAGE

Current I_L

DB1–DB16 Only

+V_S= ±12.0 V, V_L= 5.5 V

V_OL= 0 V

+V_S= ±12.0 V, V_L= 5.5 V

V_OH= 5.0 V

±100

µA

POWER SUPPLIES

Voltage Levels

+V_S

–V_S

+V_L

+10.8

–10.8

+5

+13.2

–13.2

+13.2

+10.8

–10.8

+5

+13.2

–13.2

+13.2

V

Current

+I_S

±V_S@ ±12 V

±V_S@ ±13.2 V

±V_L@ ±5.0 V

؎12

؎19

؎0.5

؎23

؎30

؎1.5

؎12

؎19

؎0.5

؎23

؎30

؎1.5

mA

+I_S

+I_L

NOTES

¹Refers to small signal bandwidth.

²Output offset dependent on value for R6.

³Refer to timing diagram.

⁴AD2S82A only.

⁵These pins are referenced to +V_S(i.e., HI = +12 V, LO = 0 V).

Specifications subject to change without notice.

All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.

–3–

REV. B

(typical @ +25؇C unless otherwise noted)

AD2S81A/AD2S82A–SPECIFICATIONS

AD2S81A

AD2S82A

Typ

Parameter

Conditions

Min

Typ

Max

Min

Max

Units

RATIO MULTIPLIER

AC Error Output Scaling

10 Bit

12 Bit

14 Bit

16 Bit

177.6

44.4

mV/Bit

44.4

11.1

2.775

PHASE SENSITIVE DETECTOR

Output Offset Voltage

Gain

12

mV

In Phase

w.r.t. REF

–0.882 –0.9

–0.918

0.04

150

–0.882 –0.9

–0.918

0.04

V rms/V dc

nA

MΩ

V

In Quadrature

Input Bias Current

Input Impedance

Input Voltage

60

150

1

±8

INTEGRATOR

Open-Loop Gain

At 10 kHz

57

100

1

60

±7

63

57

100

1

63

dB

Dead Zone Current (Hysteresis)

Input Offset Voltage

Input Bias Current

nA/LSB

mV

nA

5

150

5

150

60

Output Voltage Range

±V_S= ±10.8 V dc

±V_S= ±12 V dc

V

VCO

Maximum Rate

VCO Rate

1.0

7.1

1.1

7.9

1.0

7.1

1.1

7.9

MHz

kHz/µA

Positive DIR

Negative DIR

8.7

VCO Power Supply Sensitivity

Increase

+V_S

–V_S

+V_S

–V_S

+0.5

–8.0

+2.0

1

70

–1.22

+0.5

–8.0

+2.0

1

70

–1.22

%/V

mV

nA

nA/°C

V

Decrease

Input Offset Voltage

Input Bias Current

5

380

5

380

Input Bias Current Tempco

Input Voltage Range

Linearity of Absolute Rate

Full Range

Over 0% to 50% of Full Range

Reversion Error

Sensitivity of Reversion Error

to Symmetry of Power Supplies

VCO Output^{1, 2}

±8

<2

% FSD

%/V of

Asymmetry

V/LSB

<1

1.5

±8

±2.7

±3.0

±3.3

POWER SUPPLIES

Voltage Levels

+V_S

–V_S

+V_L

Current

+I_S

+I_L

+10.8

–10.8

+5

+13.2

–13.2

+13.2

+10.8

–10.8

+5

+13.2

–13.2

+13.2

V

±V_S@ ±12 V

±V_S@ ±13.2 V

±V_L@ ±5.0 V

؎12

؎19

؎0.5

؎23

؎30

؎1.5

؎12

؎19

؎0.5

؎23

؎30

؎1.5

mA

NOTES

¹The VCO output swings between ±3 V depending on the resolver direction.

ORDERING GUIDE

²AD2S82A only.

Operating

Specifications in boldface are tested on all production units at final electrical test.

Specifications subject to change without notice.

Temperature

Ranges

Package

Options*

Accuracy

AD2S81AJD

AD2S82AHP

AD2S82AJP

AD2S82AKP

AD2S82ALP

30 arc min

22 arc min

8 arc min

4 arc min

2 arc min

0°C to +70°C

D-28

–40°C to +85°C

P-44A

*D = Ceramic DIP Package; P = Plastic Leaded Chip Carrier (PLCC) Package.

ESD SENSITIVITY

The AD2S81A and AD2S82A features an input protection circuit consisting of large “distributed”

diodes and polysilicon series resistors to dissipate both high energy discharge (Human Body Model)

and fast, low energy pulses (Charges Device Model).

WARNING!

T

he AD2S81A and AD2S82A is ESD protection Class II (2000 V min). Proper ESD precautions are

strongly recommended to avoid functional damage or performance degradation. For further informa-

tion on ESD precautions, refer to Analog Devices ESD Prevention Manual.

ESD SENSITIVE DEVICE

–4–

REV. B

AD2S81A/AD2S82A

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS¹(with respect to GND)

+V_S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V dc

2

Power Supply Voltage (+V_Sto –V_S) . . . . . . . . . ±12 V dc ±10%

Power Supply Voltage V_L. . . . . . . . . . . . . . . . . . +5 V dc ±10%

Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms ±10%

Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak

Signal and Reference Harmonic Distortion . . . . . . . 10% (max)

Phase Shift Between Signal and Reference . ±10 Degrees (max)

Ambient Operating Temperature Range

–V_S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –14 V dc

+V_L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +V_S

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V_S

SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V_S

COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V_S

Any Logical Input . . . . . . . . . . . . . . . . . . . –0.4 V dc to +V_Ldc

Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V_S

Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V_S

VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V_S

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . .860 mW

Operating Temperature

Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial (HP, JP, KP, LP) . . . . . . . . . . . . –40°C to +85°C

PIN FUNCTION DESCRIPTIONS

Mnemonic

Description

REFERENCE I/P

DEMOD I/P

AC ERROR O/P

COS I/P

Reference Signal Input

Demodulator Input

Ratio Multiplier Output

Cosine Input

Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial (HP, JP, KP, LP) . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature (All Grades) . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

ANALOG GND

SIGNAL GND

SIN I/P

Power Ground

Resolver Signal Ground

Sine Input

CAUTION

1. Absolute Maximum Ratings are those values beyond which damage to the

device may occur.

+V_S

Positive Power Supply

2. Correct polarity voltages must be maintained on the +V_Sand –V_Spins.

DB1–DB16

+V_L

Parallel Output Data

Logic Power Supply

ENABLE

Logic Hi-Output Data in High Impedance

State Logic Lo Present Data to the Output Latches

Logic Hi-Most Significant Byte to DB1–DB8

Logic Lo-Most Significant Byte to DB1–DB8

Logic Lo Inhibits Data Transfer to Output Latches

Digital Ground

Select Converter Resolution

Logic Lo DB1–DB16 Inputs

Logic Hi DB1–DB16 Outputs

Converter Busy, Data Not Valid While Busy Hi

Logic State Defines Direction of Input Signal Rotation

Positive Pulse when Converter Output Changes from

1s to All 0s or Vice Versa

AD2S81A/AD2S82A PIN CONFIGURATIONS

BYTE SELECT

1

2

REFERENCE I/P

DEMOD I/P

AC ERROR O/P

COS I/P

28

27

26

25

DEMOD O/P

INHIBIT

DIGITAL GND

SC1–SC2*

DATA LOAD*

INTEGRATOR O/P

INTEGRATOR I/P

VCO I/P

3

4

5

24 –V

23

ANALOG GND

SIN I/P

S

BUSY

DIR

RIPPLE CLK

6

RIPPLE CLK

DIR

AD2S81A

+V

S

7

22

21

20

19

18

17

16

15

TOP VIEW

(Not to Scale)

8

MSB DB1

DB2

BUSY

9

DIGITAL GND

INHIBIT

–V_S

VCO I/P

Negative Power Supply

VCO Input

10

11

12

13

14

DB3

INTEGRATOR I/P Integrator Input

INTEGRATOR O/P Integrator Output

DEMOD O/P

COMPLEMENT*

VCO O/P*

DB4

BYTE SELECT

ENABLE

DB5

Demodulator Output

Active Logic Lo

VCO Output

+V

L

DB6

DB7

DB8 LSB

*AD2S82A Only.

Bit Weight Table

Binary

Bits (N)

Resolution Degrees

Minutes

/Bit

Seconds

/Bit

(2^N)

/Bit

0

1

2

3

4

1

2

4

8

360.0

180.0

90.0

45.0

22.5

21600.0

10800.0

5400.0

2700.0

1350.0

1296000.0

648000.0

324000.0

162000.0

81000.0

6

5

4

3

2

1

44 43 42 41 40

PIN 1

IDENTIFIER

7

8

39

38

37

36

35

34

33

SIN O/P

+V

–V

S

RIPPLE CLK

DIR

S

16

9

NC

MSB DB1

DB2

10

11

12

13

BUSY

5

6

7

8

9

32

64

128

256

512

11.25

5.625

2.8125

1.40625

0.703125

675.0

337.5

168.75

84.375

42.1875

40500.0

20250.0

10125.0

5062.5

DATA LOAD

AD2S82A

TOP VIEW

(Not to Scale)

DB3

COMPLEMENT

SC2

DB4

DB5 14

DB6 15

DB7 16

32 SC1

31

30

29

DIGITAL GND

2531.25

INHIBIT

NC

10

11

12

13

14

1024

2048

4096

8192

116384

0.3515625

0.1757813

0.0878906

0.0439453

0.0219727

21.09375

10.546875

5.273438

2.636719

1.318359

1265.625

632.8125

316.40625

158.20313

79.10156

DB8

17

18 19 20 21 22 23 24 25 26 27 28

NC = NO CONNECT

15

16

17

18

32768

65536

131072

0.0109836

0.0054932

0.0027466

0.0013733

0.659180

0.329590

0.164795

0.082397

39.55078

19.77539

9.88770

4.94385

262144

REV. B

–5–

AD2S81A/AD2S82A

CONNECTING THE CONVERTER

in Figure 7 and described in the Connecting the Resolver

section.

The power supply voltages connected to +V_Sand –V_Spins

should be +12 V dc and –12 V dc and must not be reversed.

The voltage applied to V_Lcan be +5 V dc to +V_S.

The two signal ground wires from the resolver should be joined

at the SIGNAL GROUND pin of the resolver to minimize the

coupling between the sine and cosine signals. For this reason it

is also recommended that the resolver is connected using indi-

vidually screened twisted pair cables with the sine, cosine and

reference signals twisted separately.

It is recommended that the decoupling capacitors are connected

in parallel between the power lines +V_S, –V_Sand ANALOG GND

adjacent to the converter. Recommended values are 100 nF

(ceramic) and 10 µF (tantalum). Also capacitors of 100 nF and

10 µF should be connected between +V_Land DIGITAL GND

adjacent to the converter.

SIGNAL GND and ANALOG GND are connected internally.

ANALOG GND and DIGITAL GND must be connected

externally.

When more than one converter is used on a card, then separate

decoupling capacitors should be used for each converter.

The external components required should be connected as

shown in Figures 1a and 1b.

The resolver connections should be made to the SIN and

COS inputs, REFERENCE I/P and SIGNAL GND as shown

REFERENCE I/P

OFFSET ADJUST

R9

C3

HP FILTER

–12V

+12V

R3

R8

R2

C2

C1

R1

BANDWIDTH

SELECTION

R4

C5

DEMOD

I/P

AC ERROR

O/P

DEMOD

O/P

INTEGRATOR

I/P

C4

R5

A1

A2

SIN I/P

PHASE-SENSITIVE

DETECTOR

INTEGRATOR

O/P

SEGMENT

SWITCHING

SIGNAL GND

A3

R-2R DAC

VELOCITY

SIGNAL

COS I/P

ANALOG GND

AD2S82A

R6

RIPPLE CLK

+12V

TRACKING

RATE

SELECTION

16-BIT UP/DOWN COUNTER

OUTPUT DATA LATCH

VCO

DATA TRANSFER

LOGIC

VCO I/P

–12V

R7

C6

COMP

DATA

LOAD

SC1 SC2

ENABLE

VCO DIR INHIBIT

BUSY

DIGITAL

GND

+5V

BYTE

SELECT

O/P

16 DATA BITS

Figure 1a. AD2S82A Connection Diagram

REFERENCE I/P

OFFSET ADJUST

R9

C3

R3

HP FILTER

–12V

+12V

R8

R2

C2

C1

BANDWIDTH

SELECTION

R4

R1

C5

C4

DEMOD

I/P

AC ERROR

O/P

DEMOD

O/P

INTEGRATOR

I/P

R5

PHASE-SENSITIVE

DETECTOR

INTEGRATOR

O/P

A1

A2

SIN I/P

VELOCITY

SIGNAL

SEGMENT

SWITCHING

SIGNAL GND

A3

R-2R DAC

COS I/P

AD2S81A

R6

TRACKING

RATE

SELECTION

RIPPLE CLK

+12V

16-BIT UP/DOWN COUNTER

OUTPUT DATA LATCH

VCO

DATA TRANSFER

LOGIC

VCO I/P

–12V

R7

C6

BYTE

SELECT

ENABLE

BUSY

DIGITAL

GND

+5V

DIR INHIBIT

8 DATA BITS

Figure 1b. AD2S81A Connection Diagram

–6–

REV. B

AD2S81A/AD2S82A

CONVERTER RESOLUTION (AD2S82A ONLY)

HARMONIC DISTORTION

Two major areas of the AD2S82A specification can be selected

by the user to optimize the total system performance. The reso-

lution of the digital output is set by the logic state of the inputs

SC1 and SC2 to be 10, 12, 14 or 16 bits and the dynamic char-

acteristics of bandwidth and tracking rate are selected by the

choice of external components.

The amount of harmonic distortion allowable on the signal and

reference lines is 10%.

Square waveforms can be used but the input levels should be

adjusted so that the average value is 1.9 V rms. (For example, a

square wave should be 1.9 V peak). Triangular and sawtooth

waveforms should have a amplitude of 2 V rms.

The choice of the resolution will affect the values of R4 and R6

which scale the inputs to the integrator and the VCO, respec-

tively (see the Component Selection section). If the resolution is

changed, then new values of R4 and R6 must be switched into

the circuit.

Note: The figure specified of 10% harmonic distortion is for

calibration convenience only.

POSITION OUTPUT

The resolver shaft position is represented at the converter out-

put by a natural binary parallel digital word.

Note: When changing resolution under dynamic conditions, do

it when the BUSY is low, i.e., when Data is not changing.

As the digital position output of the converter passes through

the major carries, i.e., all “1s” to all “0s” or the converse, a

RIPPLE CLK logic output is initiated indicating that a revolu-

tion or a pitch of the input has been completed.

CONVERTER OPERATION

When connected in a circuit such as shown in Figure 1, the

AD2S81A/AD2S82A operates as a tracking resolver-to-digital

converter and forms a type 2 closed loop system. The output

will automatically follow the input for speeds up to the selected

maximum tracking rate. No convert command is necessary as

the conversion is automatically initiated by each LSB increment,

or decrement, of the input. Each LSB change of the converter

initiates a BUSY pulse.

The direction of input rotation is indicated by the DIRECTION

(DIR) logic output. This direction data is always valid in ad-

vance of a RIPPLE CLK pulse and, as it is internally latched,

only changing state (1 LSB min change) with a corresponding

change in direction.

Both the RIPPLE CLK pulse and the DIR data are unaffected

by the application of the INHIBIT.

The AD2S81A/AD2S82A is remarkably tolerant of input ampli-

tude and frequency variation because the conversion depends

only on the ratio of the input signals. Consequently there is no

need for accurate, stable oscillator to produce the reference

signal. The inclusion of the phase sensitive detector in the con-

version loop ensures a high immunity to signals that are not

coherent or are in quadrature with the reference signal.

The static positional accuracy quoted is the worst case error that

can occur over the full operating temperature excluding the

effects of offset signals at the INTEGRATOR I/P (which can be

trimmed out–see Figures 1a and 1b), and with the following

conditions: input signal amplitudes are within 10% of the

nominal; phase shift between signal and reference is less than

10 degrees.

SIGNAL CONDITIONING

These operating conditions are selected primarily to establish a

repeatable acceptance test procedure which can be traced to

national standards. In practice, the AD2S81A/AD2S82A can be

used well outside these operating conditions providing the above

points are observed.

The amplitude of the SINE and COSINE signal inputs should

be maintained within 10% of the nominal values if full perfor-

mance is required from the velocity signal.

The digital position output is relatively insensitive to amplitude

variation. Increasing the input signal levels by more than 10%

will result in a loss in accuracy due to internal overload. Reduc-

ing levels will result in a steady decline in accuracy. With the

signal levels at 50% of the correct value, the angular error will

increase to an amount equivalent to 1.3 LSB. At this level the

repeatability will also degrade to 2 LSB and the dynamic re-

sponse will also change, since the dynamic characteristics are

proportional to the signal level.

VELOCITY SIGNAL

The tracking converter technique generates an internal signal at

the output of the integrator (the INTEGRATOR O/P pin) that

is proportional to the rate of change of the input angle. This is a

dc analog output referred to as the VELOCITY signal.

In many applications it is possible to use the velocity signal of

the AD2S81A/AD2S82A to replace a conventional

tachogenerator.

The AD2S81A/AD2S82A will not be damaged if the signal

inputs are applied to the converter without the power supplies

and/or the reference.

DC ERROR SIGNAL

The signal at the output of the phase-sensitive detector (DEMOD

O/P) is the signal to be nulled by the tracking loop and is, there-

fore, proportional to the error between the input angle and the

output digital angle. This is the dc error of the converter; and as

the converter is a type 2 servo loop, it will increase if the output

fails to track the input for any reason. It is an indication that the

input has exceeded the maximum tracking rate of the converter

or, due to some internal malfunction, the converter is unable to

reach a null. By connecting two external comparators, this volt-

age can be used as a “built-in test.”

REFERENCE INPUT

The amplitude of the reference signal applied to the converter’s

input is not critical, but care should be taken to ensure it is kept

within the recommended operating limits.

The AD2S81A/AD2S82A will not be damaged if the reference

is supplied to the converter without the power supplies and/or

the signal inputs.

REV. B

–7–

AD2S81A/AD2S82A

COMPONENT SELECTION

4. Maximum Tracking Rate (R6)

The following instructions describe how to select the external

components for the converter in order to achieve the required

bandwidth and tracking rate. In all cases the nearest “preferred

value’’ component should be used and a 5% tolerance will not

degrade the overall performance of the converter. Care should

be taken that the resistors and capacitors will function over the

required operating temperature range. The components should

be connected as shown in Figure 1.

The VCO input resistor R6 sets the maximum tracking rate

of the converter, and hence the velocity scaling as at the max

tracking rate, the velocity output will be 8 V.

Decide on your maximum tracking rate, “T,” in revolutions

per second. Note that “T” must not exceed the maximum

tracking rate or 1/16 of the reference frequency.

6. 32 ×10¹⁰

R6 =

Ω

PC compatible software is available to help users select the optimum

component values for the AD2S81A and AD2S82A, and display the

transfer gain, phase and small step response.

T × n

where n = bits per revolution

= 1,024 for 10 bits resolution

= 4,096 for 12 bits

= 16,384 for 14 bits

For more detailed information and explanation, see the Circuit

Functions and Dynamic Performance section.

= 65,536 for 16 bits

1. HF Filter (R1, R2, C1, C2)

The function of the HF filter is to remove any dc offset and

to reduce the amount of noise present on the signal inputs

to the AD2S81A/AD2S82A, reaching the Phase Sensitive

Detector and affecting the outputs. R1 and C2 may be omit-

ted—in which case R2 = R3 and C1 = C3, calculated below—

but their use is particularly recommended if noise from

switch mode power supplies and brushless motor drive is

present.

5. Closed-Loop Bandwidth Selection (C4, C5, R5)

a. Choose the closed-loop bandwidth (f_BW) required

ensuring that the ratio of reference frequency to band-

width does exceed the following guidelines:

Resolution

Ratio of Reference Frequency/Bandwidth

2.5 : 1

10

12

14

16

4

6

: 1

Values should be chosen so that

7.5 : 1

Typical values may be 100 Hz for a 400 Hz reference fre-

quency and 500 Hz to 1000 Hz for a 5 kHz reference

frequency.

15 kΩ ≤ R1 = R2 ≤ 56 kΩ

1

C1 = C2

b. Select C4 so that

2 π R1 f_REF

21

and f_REF= Reference Frequency

(Hz)

C4 =

F

R6 × f_BW

2

This filter gives an attenuation of three times at the input to

the phase sensitive detector.

with R6 in Ω and f_BW, in Hz selected above.

c. C5 is given by

C5 = 5 × C4 F

d. R5 is given by

2. Gain Scaling Resistor (R4)

If R1, C2 are fitted, then:

E_DC

1

3

R4 =

×

Ω

100 × 10⁻⁹

4

R5 =

Ω

2 × π × f _BW× C5

where 100 × 10^–9= current/LSB

If R1, C2 are not fitted, then:

6. VCO Phase Compensation

The following values of C6 and R7 should be fitted.

E_DC

R4 =

Ω

C6 = 470 pF, R7 = 68 Ω

100 ×10^–9

7. Offset Adjust

where E_DC= 160 × 10^–3for 10 bits resolution

Offsets and bias currents at the integrator input can cause an

additional positional offset at the output of the converter of

1 arc minute typical, 5.3 arc minutes maximum. If this can be

tolerated, then R8 and R9 can be omitted from the circuit.

= 40 × 10^–3for 12 bits

= 10 × 10^–3for 14 bits

= 2.5 × 10^–3for 16 bits

= Scaling of the DC ERROR in volts

If fitted, the following values of R8 and R9 should be used:

3. AC Coupling of Reference Input (R3, C3)

Select R3 and C3 so that there is no significant phase shift at

the reference frequency. That is,

R8 = 4.7 MΩ, R9 = 1 MΩ potentiometer

To adjust the zero offset, ensure the resolver is disconnected

and all the external components are fitted. Connect the COS

pin to the REFERENCE I/P and the SIN pin to the SIGNAL

GND and with the power and reference applied, adjust the

potentiometer to give all “0s” on the digital output bits.

R3 = 100 kΩ

1

C3 >

F

R3 × f_REF

The potentiometer may be replaced with select on test resistors

if preferred.

with R3 in Ω.

–8–

REV. B

AD2S81A/AD2S82A

DATA TRANSFER

If the AD2S81A/AD2S82A is being used in a pitch and revolu-

tion counting application, the ripple and busy will need to be

gated to prevent false decrement or increment (see Figure 2).

RIPPLE CLK is unaffected by INHIBIT.

To transfer data the INHIBIT input should be used. The data

will be valid 600 ns after the application of a logic “LO” to the

INHIBIT. This is regardless of the time when the INHIBIT is

applied and allows time for an active BUSY to clear. By using

the ENABLE input the two bytes of data can be transferred

after which the INHIBIT should be returned to a logic “HI”

state to enable the output latches to be updated.

+5V

1k⍀

10k⍀

TO COUNTER

(CLOCK)

1N414

8

RIPPLE

CLK

BUSY Output

2N3904

0V

The validity of the output data is indicated by the state of the

BUSY output. When the input to the converter is changing, the

signal appearing on the BUSY output is a series of pulses at

TTL level. A BUSY pulse is initiated each time the input moves

by the analog equivalent of one LSB and the internal counter is

incremented or decremented.

+5V

5k1

1N4148

BUSY

NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS “LO.”

Figure 2. Diode Transistor Logic Nand Gate

INHIBIT Input

The INHIBIT logic input only inhibits the data transfer from

the up-down counter to the output latches and, therefore, does

not interrupt the operation of the tracking loop. Releasing the

INHIBIT automatically generates a BUSY pulse to refresh the

output data.

DIRECTION Output

The DIRECTION (DIR) logic output indicates the direction of

the input rotation. Any change in the state of DIR precedes the

corresponding BUSY, DATA, and RIPPLE CLK updates. DIR

can be considered as an asynchronous output and can make

multiple changes in state between two consecutive LSB update

cycles. This corresponds to a change in input rotation direction

but less than 1 LSB.

ENABLE Input

The ENABLE input determines the state of the output data. A

logic “HI” maintains the output data pins in the high impedance

condition, and the application of a logic “LO” presents the data

in the latches to the output pins. The operation of the ENABLE

has no effect on the conversion process.

COMPLEMENT (AD2S82A Only)

The COMPLEMENT input is internally pulled to +12 V in the

INACTIVE STATE. It is pulled down to DIGITAL GROUND

(100 µA) to ACTIVATE.

BYTE SELECT Input

The BYTE SELECT input on the AD2S82A selects the byte of

the position data to be presented at the data output DB1 to

DB8. The least significant byte will be presented on data output

DB9 to DB16 (with the ENABLE input taken to a logic “LO”)

regardless of the state of the BYTE SELECT pin. Note that

when the AD2S82A is used with a resolution less than 16 bits,

the unused data lines are pulled to a logic “LO.” A logic “HI”

on the BYTE SELECT input will present the eight most signifi-

cant data bits on data output DB1 and DB8. A logic “LO” will

present the least significant byte on data outputs 1 to 8, i.e.,

data outputs 1 to 8 will duplicate data outputs 9 to 16.

When used in conjunction with DATA LOAD, strobing DATA

LOAD and COMPLEMENT pins to logic LO, will set the logic

HIGH bits of the AD2S82A counter to a LO state. Those bits of

the applied data which are logic LO will not change the corre-

sponding bits in the AD2S82A counter:

For Example:

Initial Counter State

Applied Data Word

Counter State after Data Load

1 0 1 0 1

1 1 0 0 0

When the BYTE select pin is a logic “HI” on the AD2S81A, the

most significant byte is presented on Pins 8 to 15 (with the

ENABLE input taken to a logic “LO”). A logic “HI” presents

the 4 least significant bits on Pins 8 to 11 and places a logic

“LO” on Pins 12 to 15 (with the ENABLE input taken to a

logic “LO”).

Initial Counter State

Applied Data Word

Counter State after Data Load and Complement 0 0 1 0 1

1 0 1 0 1

1 1 0 0 0

In order to read the output the following procedures should be

followed:

The operation of the BYTE SELECT has no effect on the con-

version process of the converter.

1. Place Outputs in high impedance (ENABLE = HI).

2. Present data to pins.

RIPPLE CLOCK

As the output of the converter passes through the major carry,

i.e., all “1s” to all “0s” or the converse, a positive going edge on

the RIPPLE CLK output is initiated indicating that a revolu-

tion, or a pitch, of the input has been completed.

3. Pull DATA LOAD and COMPLEMENT pins to ground.

4. Wait 100 ns.

5. Remove data from pins.

6. Remove outputs from high impedance state (ENABLE =

LO).

7. Read outputs.

The minimum pulsewidth of the ripple clock is 300 ns. RIPPLE

CLK is normally set high before a BUSY pulse and resets before

the next positive going edge of the next consecutive pulse.

The only exception to this is when DIR changes while the

RIPPLE CLK is high. Resetting of the RIPPLE CLK will only

occur if the DIR remains stable for two consecutive positive

BUSY pulse edges.

REV. B

–9–

AD2S81A/AD2S82A

CIRCUIT FUNCTIONS AND DYNAMIC

PERFORMANCE

V

BUSY

H

t₁

The AD2S81A/AD2S82A allows the user greater flexibility in

choosing the dynamic characteristics of the resolver-to-digital

conversion to ensure the optimum system performance. The

characteristics are set by the external components shown in

Figure 1, and the Component Selection section explains how to

select desired maximum tracking rate and bandwidth values.

The following paragraphs explain in greater detail the circuit of

the AD2S81A/AD2S82A and the variations in the dynamic

performance available to the user.

RIPPLE

CLK

V

H

L

V

t₂

H

t₃

V

t₄

H

V

DATA

H

L

t₅

V

L

INHIBIT

V

H

t₆

V

H

t₇

Loop Compensation

DIR

V

L

The AD2S81A and AD2S82A (connected as shown in Figure

1a and 1b) operates as a type 2 tracking servo loop where the

VCO/counter combination and integrator perform the two inte-

gration functions inherent in a type 2 loop.

t₈

t₉

INHIBIT

V

L

Additional compensation in the form of a pole/zero pair is re-

quired to stabilize any type 2 loop to avoid the loop gain charac-

teristic crossing the 0 dB axis with 180° of additional phase lag,

as shown in Figure 6. This compensation is implemented by the

integrator components (R4, C4, R5, C5).

V

L

ENABLE

V

t₁₀

H

V

Z

DATA

t₁₁

V

L

V

BYTE

SELECT

L

V

H

The overall response of such a system is that of a unity gain

second order low pass filter, with the angle of the resolver as the

input and the digital position data as the output.

V

H

DATA

V

L

t₁₂

t₁₃

The AD2S81A/AD2S82A does not have to be connected as

tracking converter, parts of the circuit can be used indepen-

dently. This is particularly true of the Ratio Multiplier which

can be used as a control transformer (see Application Note).

PARAMETER

T_MIN

200

10

T_MAX

600

25

CONDITION

BUSY WIDTH V_H–V_H

RIPPLE CLOCK V_HTO BUSY V_H

t₁

t₂

A block diagram of the AD2S81A/AD2S82A is given in

Figure 4.

t₃

470

16

580

45

RIPPLE CLOCK V_LTO NEXT BUSY V_H

BUSY V_HTO DATA V_H

t₄

t₅

3

25

BUSY V_HTO DATA V_L

t₆

70

140

625

670

600

110

140

125

INHIBIT V_HTO BUSY V_H

t₇

485

515

–

MIN DIR V_HTO BUSY V_H

t₈

MIN DIR V_HTO BUSY V_H

t₉

INHIBIT V_LTO DATA STABLE

ENABLE V_LTO DATA V_H

t₁₀

t₁₁

t₁₂

t₁₃

40

35

ENABLE V_LTO DATA V_L

60

BYTE SELECT V_LTO DATA STABLE

BYTE SELECT V_HTO DATA STABLE

60

Figure 3. Digital Timing

C5

R5

AC ERROR

C4

sin ␪ sin ␻t

R4

PHASE-

SENSITIVE

DEMODULATOR

RATIO

MULTIPLIER

A1 sin (␪ – ␾) sin ␻t

cos ␪ sin ␻t

INTEGRATOR

R6

CLOCK

VCO

VELOCITY

DIRECTION

DIGITAL

␾

Figure 4. AD2S81A/AD2S82A Functional Diagram

–10–

REV. B

AD2S81A/AD2S82A

Ratio Multiplier

Phase Sensitive Demodulator

The ratio multiplier is the input section of the AD2S81A/

AD2S82A and compares the signal from the resolver input

angle, θ, to the digital angle, φ, held in the counter. Any differ-

ence between these two angles results in an analog voltage at

the AC ERROR OUTPUT. This circuit function has histori-

cally been called a “Control Transformer” as it was originally

performed by an electromechanical device known by that name.

The phase sensitive demodulator is effectively ideal and devel-

ops a mean dc output at the DEMODULATOR O/P pin of

±2 2

π

×(DEMODULATOR I/P rms voltage)

for sinusoidal signals in phase or antiphase with the reference

(for a square wave the DEMODULATOR O/P voltage will

equal the DEMODULATOR I/P). This provides a signal at the

DEMODULATOR O/P which is a dc level proportional to the

positional error of the converter.

The AC ERROR signal is given by

A1 sin (θ – φ) sin ωt

where ω = 2 π f_REF

DC Error Scaling = 160 mV/bit (10-bits resolution)

f_{REF =}reference frequency

= 40 mV/bit (12-bits resolution)

= 10 mV/bit (14-bits resolution)

= 2.5 mV/bit (16-bits resolution)

A1, the gain of the ratio multiplier stage is 14.5.

So for 2 V rms inputs signals

AC ERROR output in volts/(bit of error)

When the tracking loop is closed, this error is nulled to zero

unless the converter input angle is accelerating.

360

n

Integrator

= 2 × sin

Where n = bits per rev

× A1

The integrator components (R4, C4, R5, C5) are external to

the AD2S81A/AD2S82A to allow the user to determine the

optimum dynamic characteristics for any given application. The

Component Selection section explains how to select compo-

nents for a chosen bandwidth.

= 1,024 for 10-bits resolution

= 4,096 for 12 bits

= 16,384 for 14 bits

Since the output from the integrator is fed to the VCO INPUT,

it is proportional to velocity (rate of change of output angle)

and can be scaled by selection of R6, the VCO input resistor.

This is explained in the Voltage Controlled Oscillator (VCO)

section below.

= 65,536 for 16 bits

Giving an AC ERROR O/P

= 178 mV/bit @ 10-bits resolution

= 44.5 mV/bit @ 12 bits

= 11.125 mV/bit @ 14 bits

= 2.78 mV/bit @ 16 bits

To prevent the converter from “flickering” (i.e., continually

toggling by ±1 bit when the quantized digital angle, φ, is not an

exact representation of the input angle, θ), feedback is internally

applied from the VCO to the integrator input to ensure that the

VCO will only update the counter when the error is greater than

or equal to 1 LSB. In order to ensure that this feedback “hyster-

esis” is set to 1 LSB the input current to the integrator must be

scaled to be 100 nA/bit. Therefore,

The ratio multiplier will work in exactly the same way whether

the AD2S81A/AD2S82A is connected as a tracking converter or

as a control transformer, where data is preset into the counters

using the DATA LOAD pin.

HF Filter

The AC ERROR OUTPUT may be fed to the PSD via a simple

ac coupling network (R2, C1) to remove any dc offset at this

point. Note, however, that the PSD of the AD2S81A/AD2S82A

is a wideband demodulator and is capable of aliasing HF noise

down to within the loop bandwidth. This is most likely to hap-

pen where the resolver is situated in particularly noisy environ-

ments, and the user is advised to fit a simple HF filter R1, C2

prior to the phase sensitive demodulator.

DC Error Scaling (mV/bit )

R4 =

100 (nA/bit )

Any offset at the input of the integrator will affect the accuracy

of the conversion as it will be treated as an error signal and

offset the digital output. One LSB of extra error will be

added for each 100 nA of input bias current. The method of

adjusting out this offset is given in the Component Selection

section.

The attenuation and frequency response of a filter will affect the

loop gain and must be taken into account in deriving the loop

transfer function. The suggested filter (R1, C1, R2, C2) is shown

in Figure 1 and gives an attenuation at the reference frequency

(f_REF) of 3 times at the input to the phase sensitive demodulator.

Voltage Controlled Oscillator (VCO)

The VCO is essentially a simple integrator feeding a pair of dc

level comparators. Whenever the integrator output reaches one

of the comparator threshold voltages, a fixed charge is injected

into the integrator input to balance the input current. At the

same time the counter is clocking either up or down, dependent

on the polarity of the input current. In this way the counter is

clocked at a rate proportional to the magnitude of the input

current of the VCO.

Values of components used in the filter must be chosen to en-

sure that the phase shift at f_REFis within the allowable signal to

reference phase shift of the converter.

REV. B

–11–

AD2S81A/AD2S82A

Figure 5 illustrates how the VCO output compensates for in-

stances where, due to hysteresis, there is no change in the digital

count output for 1 LSB change in input angle. The sum of the

digital count output and VCO output equals the actual input

angle.

During the reset period the input continues to be integrated, the

reset period is constant at 400 ns.

The VCO rate is fixed for a given input current by the VCO

scaling factor:

= 7. 9 kHz / µA

Transfer Function

The tracking rate in rps per µA of VCO input current can be

found by dividing the VCO scaling factor by the number of LSB

changes per rev (i.e., 4096 for 12-bit resolution).

By selecting components using the method outlined in the

Component Selection section, the converter will have a critically

damped time response and maximum phase margin. The

Closed-Loop Transfer Function is given by:

The input resistor R6 determines the scaling between the con-

verter velocity signal voltage at the INTEGRATOR O/P pin and

the VCO input current. Thus to achieve a 5 V output at 100 rps

(6000 rpm) and 12-bit resolution the VCO input current must

be:

(100 × 4096)/(7900) = 51.8 µA

Thus, R6 would be set to: 5/(51.8 × 10^-–6) = 96 kΩ

θ_OUT

θ_IN

14(1+ s_N)

(s_N+ 2.4)(s_N+ 3.4 s_N+ 5.8)

=

2

where S_N, the normalized frequency variable, is:

2

π

s

S_N=

f _BW

The velocity offset voltage depends on the VCO input resistor,

R6, and the VCO bias current and is given by

and f_BWis the closed loop 3 dB bandwidth (selected by the

choice of external components).

Velocity Offset Voltage = R6 × (VCO bias current )

The temperature coefficient of this offset is given by

Velocity Offset Tempco = R6 × (VCO bias current tempco)

where the VCO bias current tempco is typically –1.22 nA/°C.

The acceleration constant, K_A, is given approximately by

K _A= 6 × ( f _BW)²sec⁻²

The normalized gain and phase diagrams are given in Figures

6 and 7.

The maximum recommended rate for the VCO is 1.1 MHz

which sets the maximum possible tracking rate.

12

9

Since the minimum voltage swing available at the integrator

output is ±8 V, this implies that the minimum value for R6 is

57 kΩ. As

6

1. 1 × 10⁶

7. 9 × 10³

3

Max Current =

MinValue R6 =

= 139 µA

= 57kΩ

0

–3

–6

–9

–12

8

139 ×10⁻⁶

VCO OUTPUT

In order to overcome the “freeplay” inherent in a servo system

using digitized position feedback, an analog output voltage is

available representing the resolver shaft position within the least

significant bit of digital angle output.

0.02

0.04

0.1

0.2

0.4

0

2

FREQUENCY – f_BW

Figure 6. AD2S81A/AD2S82A Gain Plot

The converter updates the output if the error is an LSB or

greater and the VCO output gives the positional error smaller

than 1 LSB.

180

135

90

45

0

INPUT

ANGLE

+LSB

–45

–90

0

–LSB

–135

+3V

–180

VCO

0.02

0.04

0.1

0.2

0.4

0

2

OUTPUT

FREQUENCY – f_BW

–3V

Figure 7. AD2S81A/AD2S82A Phase Plot

Figure 5.

–12–

REV. B

AD2S81A/AD2S82A

The small signal step response is shown in Figure 8. The time

from the step to the first peak is t₁and the t₂is the time from

the step until the converter is settled to 1 LSB. The times t₁and

t₂are given approximately by

Input Acceleration[LSB/sec²]

Error in LSBs =

K_A[sec^–2

]

100[rev/sec²] × 2¹²

2.7×10⁶

=

= 0.15LSBs or 47.5seconds of arc

1

t₁=

f _BW

To determine the value of K_Abased on the passive components

used to define the dynamics of the converter, the following

should be used:

5

R

t₂=

×

f _BW12

4.04 × 10¹¹

2ⁿR6 R4 (C4 + C5)

K _A

=

where R = resolution, i.e., 10, 12, 14 or 16.

OUTPUT

POSITION

t₂

Where n = resolution of the converter

R4, R6 in ohms

C5, C4 in farads

SOURCES OF ERRORS

Integrator Offset

Additional inaccuracies in the conversion of the resolver signals

will result from an offset at the input to the integrator as it will

be treated as an error signal. This error will typically be 1 arc

minute over the operating temperature range.

TIME

t₁

A description of how to adjust from zero offset is given in the

Component Selection section and the circuit required is shown

in Figures 1a and 1b.

Figure 8. AD2S81A/AD2S82A Small Step Response

The large signal step response (for steps greater than 5 degrees)

applies when the error voltage exceeds the linear range of the

converter.

Differential Phase Shift

Phase shift between the sine and cosine signals from the resolver

is known as differential phase shift and can cause static error.

Some differential phase shift will be present on all resolvers as a

result of coupling. A small resolver residual voltage (quadrature

voltage) indicates a small differential phase shift. Additional

phase shift can be introduced if the sine channel wires and the

cosine channel wires are treated differently. For instance, differ-

ent cable lengths or different loads could cause differential

phase shift.

Typically the converter will take three times longer to reach the

first peak for a 179 degrees step.

In response to a velocity step, the velocity output will exhibit

the same time response characteristics as outlined above for the

position output.

ACCELERATION ERROR

A tracking converter employing a type 2 servo loop does not

suffer any velocity lag, however, there is an additional error due

to acceleration. This additional error can be defined using the

acceleration constant K_Aof the converter.

The additional error caused by differential phase shift on the

input signals approximates to

Error = 0.53 a × b arc minutes

where a = differential phase shift (degrees).

b = signal to reference phase shift (degrees).

Input Acceleration

K _A

=

Error in Output Angle

This error can be minimized by choosing a resolver with a small

residual voltage, ensuring that the sine and cosine signals are

handled identically and removing the reference phase shift (see

Connecting the Resolver section). By taking these precautions

the extra error can be made insignificant.

The numerator and denominator must have consistent angular

units. For example, if K_Ais in sec^–2, then the input acceleration

may be specified in degrees/sec²and the error output in degrees.

Angular measurement may also be specified using radians, min-

utes of arc, LSBs, etc.

Under static operating conditions phase shift between the refer-

ence and the signal lines alone will not theoretically affect the

converter’s static accuracy.

K_Adoes not define maximum input acceleration, only the error due

to it’s acceleration. The maximum acceleration allowable before

the converter loses track is dependent on the angular accuracy

requirements of the system.

However, most resolvers exhibit a phase shift between the signal

and the reference. This phase shift will give rise under dynamic

conditions to an additional error defined by:

Angular Accuracy × K_A= degrees/sec²

K_Acan be used to predict the output position error for a given

input acceleration. For example for an acceleration of 100 revs/

sec², K_A= 2.7 × 10⁶sec^–2and 12-bit resolution.

Shaft Speed (rps) × Phase Shift (Degrees)

Reference Frequency

REV. B

–13–

AD2S81A/AD2S82A

Following the preceding precautions will allow the user to use

the velocity signal in very noisy environments for example PWM

motor drive applications. Resolver/converter error curves may

exhibit apparent acceleration/deceleration at a constant velocity.

This results in ripple on the velocity signal of frequency twice

the input rotation.

For example, for a phase shift of 20 degrees, a shaft rotation of

22 rps and a reference frequency of 5 kHz, the converter will

exhibit an additional error of:

22×20

0.088 degrees

5000

This effect can be eliminated by putting a phase shift in the

reference to the converter equivalent to the phase shift in the

resolver (see Connecting the Resolver section).

CONNECTING THE RESOLVER

The recommended connection circuit is shown in Figure 9.

Note: Capacitive and inductive crosstalk in the signal and reference

leads and wiring can cause similar problems.

OSCILLATOR

(e.g. OSC1758)

C3

VELOCITY ERRORS

REF I/P

1

2

3

4

5

6

7

The signal at the INTEGRATOR O/P pin relative to the ANA-

LOG GND pin is an analog voltage proportional to the rate of

change of the input angle. This signal can be used to stabilize

servo loops or in the place of a velocity transducer. Although the

conversion loop of the AD2S81A/AD2S82A includes a digital

section, there is an additional analog feedback loop around the

velocity signal. This ensures against flicker in the digital posi-

tional output in both dynamic and static states.

R3

AD2S82A

TWISTED PAIR

SCREENED

CABLE

DIGITAL

GND

31

COS I/P

ANALOG

GND

SIGNAL

GND

S2

R1

S4

S3

SIN I/P

A better quality velocity signal will be achieved if the following

points are considered:

R2

S1

RESOLVER

1. Protection.

POWER RETURN

The velocity signal should be buffered before use.

Figure 9. Connecting the AD2S82A to a Resolver

2. Reversion error*

The reversion error can be nulled by varying one supply rail

relative to the other.

In cases where the reference phase relative to the input signals

from the resolver requires adjustment, this can be easily

achieved by varying the value of the resistor R2 of the HF filter

(see Figures 1a and 1b).

3. Ripple and Noise.

Noise on the input signals to the converter is the major cause of

noise on the velocity signal. This can be reduced to a minimum

if the following precautions are taken:

Assuming that R1 = R2 = R and C1 = C2 = C

1

The resolver is connected to the converter using separate

twisted pair cable for the sine, cosine and reference signals.

and Reference Frequency =

2 π RC

Care is taken to reduce the external noise wherever possible.

by altering the value of R2, the phase of the reference relative to

the input signals will change in an approximately linear manner

for phase shifts of up to 10 degrees.

An HF filter is fitted before the Phase-Sensitive Demodulator

(as described in the section HF FILTER).

Increasing R2 by 10% introduces a phase lag of 2 degrees. De-

creasing R2 by 10% introduces a phase lead of 2 degrees.

A resolver is chosen that has low residual voltage, i.e., a small

signal in quadrature with the reference.

Components are selected to operate the AD2S81A/AD2S82A

with the lowest acceptable bandwidth.

1

PHASE LEAD = ARC TAN

C

PHASE LAG = ARC TAN 2 ␲ fRC

2 ␲ fRC

R

Feedthrough of the reference frequency should be removed

by a filter on the velocity signal.

R

C

Maintenance of the input signal voltages at 2 V rms will

prevent LSB flicker at the positional output. The analog

feedback or hysteresis employed around the VCO and the

integrator is a function of the input signal levels (see Integra-

tor section).

Figure 10. Phase Shift Circuits

^*Reversion error, or side-to-side nonlinearity, is a result of differences in the up and

down rates of the VCO.

–14–

REV. B

AD2S81A/AD2S82A

1M⍀

100k⍀

22nF

15k⍀

100nF

4.7M⍀

REFERENCE

INPUT

VELOCITY

O/P

100nF

22nF

15k⍀

1.5nF

6.8nF

39k⍀

110k⍀

68⍀

180k⍀

COS HIGH

REF LOW

COS LOW

SIN LOW

RESOLVER

SIGNAL

470pF

100nF

6

7

5

4

3

2

1

44 43 42 41 40

–12V

39

38

37

36

35

34

33

32

31

SIN HIGH

+12V

PIN 1

IDENTIFIER

RIPPLE CLK

DIRECTION

BUSY

8

9

MSB

10

11

12

13

14

15

16

17

DATA LOAD

AD2S82A

TOP VIEW

(Not to scale)

COMPLEMENT

SC2

DATA

OUTPUT

0V

30 INHIBIT

29

18 19 20 21 22 23 24 25 26 27 28

LSB

BYTE SELECT

ENABLE

DATA OUTPUT

+5V

Figure 11. Typical Circuit Configuration

TYPICAL CIRCUIT CONFIGURATION

For more information on resistive scaling of SIN, COS and

REFERENCE converter inputs, refer to the application note

“Circuit Applications of the 2S81 and 2S80 Resolver-to-Digital

Converters.”

Figure 11 shows a typical circuit configuration for the AD2S81A/

AD2S82A in a 12-bit resolution mode. Values of the external

components have been chosen for a reference frequency of 5 kHz

and a maximum tracking rate of 260 rps with a bandwidth of

520 Hz. Placing the values for R4, R6, C4 and C5 in the equa-

tion for K_Agives a value of 2.7 × 10⁶. The resistors are 0.125 W,

5% tolerance preferred values. The capacitors are 100 V ceramic,

10% tolerance components.

APPLICATIONS

Control Transformer

The ratio multiplier of the AD2S82A can be used independently

of the loop integrators as a control transformer. In this mode the

resolver inputs θ are multiplied by a digital angle φ, any differ-

ence between and φ and θ will be represented by the AC ERROR

output as SIN ωt sin (θ–φ) or the DEMOD output as sin (θ–φ).

To use the AD2S81A/AD2S82A in this mode refer to the

“Control Transformer” application note.

For signal and reference voltages greater than 2 V rms a simple

voltage divider circuit of resistors can be used to generate the

correct signal level at the converter. Care should be taken to

ensure that the ratios of the resistors between the sine signal line

and ground and the cosine signal line and ground are the same.

Any difference will result in an additional position error.

Dynamic Switching

In applications where the user requires wide band response from

the converter, for example 100 rpm to 6000 rpm, superior per-

formance is achieved if the converters control characteristics are

switched dynamically. This reduces velocity offset levels at low

tracking rates. For more information on the technique refer to

“Dynamic Resolution Switching Using the Variable Resolution

Monolithic Resolver-to-Digital Converters.”

360

315

270

225

180

OTHER PRODUCTS

The AD2S80A is a monolithic resolver-to-digital converter

offering 10–16 bits of resolution and user selectable dynamics.

The AD2S80A is also available in 40-lead ceramic DIP, 44-lead

LCC and is qualified to MIL-STD 883B Rev C.

135

90

45

0

The AD2S46 is a highly integrated hybrid resolver/synchro to

digital converter packaged in a 28-lead ceramic DIP. The part

offers the user 1.3 arc minutes of accuracy over the full military

temperature range.

0

4

8

12

16

20

24

TIME – ms

Figure 12. Large Step Response Curves for Typical Circuit

Shown in Figure 11

The AD2S34 is a dual channel 14-bit hybrid resolver-to-digital

converter packaged in a 1 in²32-lead flatpack.

The 1740/41/42 are hybrid resolver/synchro to digital converters

which incorporate pico-transformer isolated input signal

conditioning.

REV. B

–15–

AD2S81A/AD2S82A

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Ceramic DIP (D) Package

(D-28)

0.005 (0.13) MIN

28

0.100 (2.54) MAX

15

0.610 (15.49)

0.500 (12.70)

1

14

0.620 (15.75)

0.590 (14.99)

PIN 1

1.490 (37.85) MAX

0.060 (1.52)

0.225

(5.72)

MAX

0.015 (0.38)

0.150

(3.81)

MIN

0.018 (0.46)

0.008 (0.20)

0.200 (5.08)

0.125 (3.18)

SEATING

PLANE

0.026 (0.66) 0.110 (2.79) 0.070 (1.78)

0.014 (0.36) 0.090 (2.29) 0.030 (0.76)

Plastic Leaded Chip Carrier (P) Package

(P-44A)

0.180 (4.57)

0.165 (4.19)

0.056 (1.42)

0.042 (1.07)

0.048 (1.21)

0.042 (1.07)

0.025 (0.63)

0.015 (0.38)

0.048 (1.21)

0.042 (1.07)

6

40

39

7

PIN 1

IDENTIFIER

0.050

(1.27)

BSC

0.63 (16.00)

0.59 (14.99)

0.021 (0.53)

0.013 (0.33)

TOP VIEW

(PINS DOWN)

0.032 (0.81)

0.026 (0.66)

17

29

28

18

0.040 (1.01)

0.025 (0.64)

0.020

(0.50)

R

0.656 (16.66)

0.650 (16.51)

SQ

0.110 (2.79)

0.085 (2.16)

0.695 (17.65)

0.685 (17.40)

–16–

REV. B

型号:	AD2S81AJD
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Active
零件包装代码：	DIP
包装说明：	DIP,
针数：	28
Reach Compliance Code：	unknown
风险等级：	5.9
Is Samacsys：	N
其他特性：	LG-MAX
最大模拟输入电压：	2 V
最大角精度：	30 arc min
转换器类型：	SYNCHRO OR RESOLVER TO DIGITAL CONVERTER
JESD-30 代码：	R-CDIP-T28
JESD-609代码：	e0
长度：	37.85 mm
湿度敏感等级：	NOT SPECIFIED
最大负电源电压：	-13.2 V
最小负电源电压：	-10.8 V
标称负供电电压：	-12 V
位数：	12
功能数量：	1
端子数量：	28
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	COMMERCIAL
座面最大高度：	5.27 mm
信号/输出频率：	20000 Hz
最大供电电压：	13.2 V
最小供电电压：	10.8 V
标称供电电压：	12 V
表面贴装：	NO
技术：	BICMOS
温度等级：	COMMERCIAL
端子面层：	TIN LEAD
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
最大跟踪速率：	260 rps
宽度：	15.24 mm
Base Number Matches：	1

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