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I²C-Compatible,

256-Position Digital Potentiometers

AD5241/AD5242

FEATURES

FUNCTIONAL BLOCK DIAGRAM

A

W

B

O

2

1

256 positions

10 kΩ, 100 kΩ, 1 MΩ

SHDN

Low temperature coefficient: 30 ppm/°C

Internal power on midscale preset

Single-supply 2.7 V to 5.5 V or dual-supply 2.7 V for ac or

bipolar operation

V

DD

RDAC

REGISTER 1

REGISTER 2

V

SS

I²C-compatible interface with readback capability

Extra programmable logic outputs

Self-contained shutdown feature

Extended temperature range: −40°C to +105°C

ADDR

DECODE

8

AD5241

SDA

SCL

GND

PWR-ON

RESET

SERIAL INPUT REGISTER

APPLICATIONS

AD1

AD0

Multimedia, video, and audio

Figure 1. AD5241 Functional Block Diagram

Communications

Mechanical potentiometer replacement

Instrumentation: gain, offset adjustment

Programmable voltage-to-current conversion

Line impedance matching

A

W

B

A

W

B

O

2

1

2

1

SHDN

REGISTER

V

DD

RDAC

REGISTER 1

RDAC

REGISTER 2

V

SS

ADDR

DECODE

AD5242

8

1

SDA

SCL

GND

PWR-ON

RESET

SERIAL INPUT REGISTER

AD0

AD1

Figure 2. AD5242 Functional Block Diagram

GENERAL DESCRIPTION

The AD5241/AD5242 provide a single-/dual-channel, 256-

position, digitally controlled variable resistor (VR) device. These

devices perform the same electronic adjustment function as a

potentiometer, trimmer, or variable resistor. Each VR offers a

completely programmable value of resistance between the A

terminal and the wiper, or the B terminal and the wiper. For the

AD5242, the fixed A-to-B terminal resistance of 10 kΩ, 100 kΩ,

or 1 MΩ has a 1% channel-to-channel matching tolerance. The

nominal temperature coefficient of both parts is 30 ppm/°C.

Wiper position programming defaults to midscale at system

power on. When powered, the VR wiper position is programmed

by an I²C®-compatible, 2-wire serial data interface. Both parts

have two extra programmable logic outputs available that

enable users to drive digital loads, logic gates, LED drivers, and

analog switches in their system.

The AD5241/AD5242 are available in surface-mount, 14-lead

SOIC and 16-lead SOIC packages and, for ultracompact solutions,

14-lead TSSOP and 16-lead TSSOP packages. All parts are

guaranteed to operate over the extended temperature range of

−40°C to +105°C.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD5241/AD5242

TABLE OF CONTENTS

Features .............................................................................................. 1

Test Circuits..................................................................................... 11

Theory of Operation ...................................................................... 12

Programming the Variable Resistor......................................... 12

Programming the Potentiometer Divider............................... 13

Digital Interface.......................................................................... 13

Readback RDAC Value.............................................................. 14

Multiple Devices on One Bus ................................................... 14

Level-Shift for Bidirectional Interface..................................... 14

Additional Programmable Logic Output................................ 15

Shutdown Function.................................................................... 15

Outline Dimensions....................................................................... 16

Ordering Guide .......................................................................... 18

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

10 kΩ, 100 kΩ, 1 MΩ Version .................................................... 3

Timing Diagrams.......................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

12/09—Rev. B to Rev. C

2/02—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

Changes to 10 kΩ, 100 kΩ, 1 MΩ Version Section...................... 3

Changes to Table 3............................................................................ 6

Deleted Digital Potentiometer Selection Guide Section ........... 14

Changed Self-Contained Shutdown Function Section to

Shutdown Function Section.......................................................... 15

Changes to Shutdown Function Section ..................................... 15

Changes to Ordering Guide .......................................................... 18

Edits to Features.................................................................................1

Edits to Functional Block Diagrams...............................................1

Edits to Absolute Maximum Ratings..............................................4

Changes to Ordering Guide.............................................................4

Edits to Pin Function Descriptions.................................................5

Edits to Figures 1, 2, 3.......................................................................6

Added Readback RDAC Value Section, Additional

Programmable Logic Output Section, and Figure 7;

Renumbered Sequentially ............................................................. 11

Changes to Digital Potentiometer Selection Guide ................... 14

8/02—Rev. A to Rev. B

Additions to Features ....................................................................... 1

Changes to General Description .................................................... 1

Changes to Specifications................................................................ 2

Changes to Absolute Maximum Ratings....................................... 4

Additions to Ordering Guide.......................................................... 4

Changes to TPC 8 and TPC 9 ......................................................... 8

Changes to Readback RDAC Value Section................................ 11

Changes to Additional Programmable Logic Output Section.. 11

Added Self-Contained Shutdown Section................................... 12

Added Figure 8................................................................................ 12

Changes to Digital Potentiometer Selection Guide ................... 14

Rev. C | Page 2 of 20

AD5241/AD5242

SPECIFICATIONS

10 kΩ, 100 kΩ, 1 MΩ VERSION

V_DD= 2.7 V to 5.5 V, V_A= V_DD, V_B= 0 V, −40°C < T_A< +105°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS, RHEOSTAT MODE

(SPECIFICATIONS APPLY TO ALL VRs)

Resolution

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance

N

8

Bits

LSB

%

R-DNL

R-INL

ΔR_AB/R_AB

R_WB, V_A= no connect

T_A= 2ꢁ°C, R_AB= 10 kΩ

−1

−2

−30

0.ꢀ

0.ꢁ

+1

+2

+30

+ꢁ0

T_A= 2ꢁ°C,

%

R_AB= 100 kΩ/1 MΩ

Resistance Temperature Coefficient

Wiper Resistance

(ΔR_AB/R_AB)/

ΔT × 10⁶

R_W

V_AB= V_DD, wiper =

no connect

I_W= V_DD/R

30

60

ppm/°C

Ω

120

DC CHARACTERISTICS, POTENTIOMETER DIVIDER

MODE (SPECIFICATIONS APPLY TO ALL VRs)

Resolution

N

8

Bits

Differential Nonlinearity³

Integral Nonlinearity³

Voltage Divider Temperature Coefficient

Full-Scale Error

DNL

INL

−1

−2

0.ꢀ

0.ꢁ

ꢁ

−0.ꢁ

0.ꢁ

+1

+2

LSB

ppm/°C

LSB

(ΔV_W/V_W)/∆T × 10⁶Code = 0x80

V_WFSE

V_WZSE

Code = 0xFF

Code = 0x00

−1

0

1

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range^ꢀ

V_A, V_B, V_W

C_A, C_B

V_SS

V_DD

V

pF

Capacitance (A, B)^ꢁ

f = 1 MHz, measured

to GND, code = 0x80

f = 1 MHz, measured

to GND, code = 0x80

ꢀꢁ

60

1

Capacitance (W)^ꢁ

C_W

I_CM

pF

Common-Mode Leakage

DIGITAL INPUTS

V_A= V_B= V_W

nA

Input Logic High (SDA and SCL)

Input Logic Low (SDA and SCL)

Input Logic High (AD0 and AD1)

Input Logic Low (AD0 and AD1)

Input Logic High

Input Logic Low

Input Current

Input Capacitance^ꢁ

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

I_IL

C_IL

V_OL

V_OH

I_OZ

0.7 × V_DD

V_DD+ 0.ꢁ V

+0.3 × V_DD

V

μA

pF

V

μA

pF

−0.ꢁ

2.ꢀ

0

2.1

0

V_DD= ꢁ V

V_DD= 3 V

V_DD

0.8

V_DD

0.6

1

V_IH= ꢁ V or V_IL= GND

3

DIGITAL OUTPUT

I_OL= 3 mA

I_OL= 6 mA

I_SINK= 1.6 mA

I_SOURCE= ꢀ0 μA

V_IH= ꢁ V or V_IL= GND

0.ꢀ

0.6

0.ꢀ

Output Logic Low (SDA)

Output Logic Low (O₁and O₂)

Output Logic High (O₁and O₂)

Three-State Leakage Current (SDA)

Output Capacitance^ꢁ

ꢀ

1

8

C_OZ

POWER SUPPLIES

Power Single-Supply Range

Power Dual-Supply Range

Positive Supply Current

Negative Supply Current

Power Dissipation⁶

V_{DD RANGE}

V_DD/V_{SS RANGE}

I_DD

I_SS

P_DISS

V_SS= 0 V

2.7

2.3

ꢁ.ꢁ

2.7

ꢁ0

−ꢁ0

2ꢁ0

V

μA

V_IH= ꢁ V or V_IL= GND

V_SS= −2.ꢁ V, V_DD= +2.ꢁ V

V_IH= ꢁ V or V_IL= GND,

0.1

+0.1

0.ꢁ

μW

V_DD= ꢁ V

Power Supply Sensitivity

PSS

−0.01

+0.002 +0.01

%/%

Rev. C | Page 3 of 20

AD5241/AD5242

Parameter

DYNAMIC CHARACTERISTICS^{ꢁ, 7, 8}

Symbol

Conditions

Min

Typ¹

Max

Unit

−3 dB Bandwidth

BW_10 kΩ

BW_100 kΩ

BW_1 MΩ

THD_W

R_AB= 10 kΩ, code = 0x80

R_AB= 100 kΩ, code = 0x80

R_AB= 1 MΩ, code = 0x80

V_A= 1 V rms + 2 V dc,

V_B= 2 V dc, f = 1 kHz

6ꢁ0

69

6

kHz

%

Total Harmonic Distortion

V_WSettling Time

0.00ꢁ

t_S

V_A= V_DD, V_B= 0 V, 1 LSB

error band, R_AB= 10 kΩ

2

μs

Resistor Noise Voltage

e_{N_WB}

R_WB= ꢁ kΩ, f = 1 kHz

1ꢀ

nV√Hz

INTERFACE TIMING CHARACTERISTICS

(APPLIES TO ALL PARTS^{ꢁ, 9}

SCL Clock Frequency

Bus Free Time Between Stop and Start, t_BUF

)

f_SCL

t₁

0

1.3

ꢀ00

kHz

μs

Hold Time (Repeated Start), t_{HD; STA}

t₂

After this period, the first 600

clock pulse is generated

ns

Low Period of SCL Clock, t_LOW

High Period of SCL Clock, t_HIGH

Setup Time for Repeated Start Condition, t_{SU; STA}

Data Hold Time, t_{HD; DAT}

Data Setup Time, t_{SU; DAT}

Rise Time of Both SDA and SCL Signals, t_R

t₃

t_ꢀ

t_ꢁ

t₆

t₇

t₈

1.3

0.6

600

μs

ns

ꢁ0

900

100

300

Fall Time of Both SDA and SCL Signals, t_F

Setup Time for Stop Condition, t_{SU; STO}

t₉

t₁₀

ns

¹Typicals represent average readings at 2ꢁ°C, V_DD= ꢁ V.

²Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits.

³INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V_A= V_DDand V_B= 0 V. DNL

specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 37.

^ꢀResistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

^ꢁGuaranteed by design, not subject to production test.

⁶P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

⁷Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

⁸All dynamic characteristics use V_DD= ꢁ V.

⁹See timing diagram in Figure 3 for location of measured values.

Rev. C | Page ꢀ of 20

AD5241/AD5242

TIMING DIAGRAMS

t₈

SDA

SCL

t₁

t₈

t₉

t₂

t₄

t₂

t₇

t₅

t₁₀

t₃

P

S

P

t₆

Figure 3. Detail Timing Diagram

Data of AD5241/AD5242 is accepted from the I²C bus in the following serial format.

Table 2.

W

R/

A

/B

S

0

1

0

1

AD1 AD0

A

RS SD O₁O₂

Instruction Byte

X

A

D7 D6 D5 D4 D3 D2 D1 D0

Data Byte

A

P

Slave Address Byte

where:

S = start condition

P = stop condition

A = acknowledge

X = don’t care

AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at Pins AD1 and AD0.

W

R/ = Read enable at high and output to SDA. Write enable at low.

A

/B = RDAC subaddress select; 0 for RDAC1 and 1 for RDAC2.

RS = Midscale reset, active high.

SHDN

SD = Shutdown in active high. Same as

except inverse logic.

O₁, O₂= Output logic pin latched values

D7, D6, D5, D4, D3, D2, D1, D0 = data bits.

1

9

1

9

1

9

SCL

O

2

AD1 AD0

0

1

R/W

A/B RS SD

X

D7 D6 D5 D4 D3 D2 D1 D0

SDA

1

ACK BY

AD5241

ACK BY

AD5241

ACK BY

AD5241

STOP BY

MASTER

START BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

Figure 4. Writing to the RDAC Serial Register

1

9

1

9

SCL

0

AD1 AD0

1

R/W

D7 D6 D5 D4 D3 D2 D1 D0

NO ACK BY

SDA

ACK BY

AD5241

MASTER

STOP BY

MASTER

START BY

MASTER

FRAME 2

FRAME 1

SLAVE ADDRESS BYTE

DATA BYTE FROM PREVIOUSLY SELECTED

RDAC REGISTER IN WRITE MODE

Figure 5. Reading Data from a Previously Selected RDAC Register in Write Mode

Rev. C | Page ꢁ of 20

AD5241/AD5242

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

Rating

V_DDto GND

V_SSto GND

V_DDto V_SS

−0.3 V to +7 V

0 V to −7 V

7 V

V_A, V_B, V_Wto GND

I_A, I_B, I_W

V_SSto V_DD

ꢁ.0 mA¹

ESD CAUTION

R_AB= 10 kΩ in TSSOP-1ꢀ

R_AB= 100 kΩ in TSSOP-1ꢀ

R_AB= 1 MΩ in TSSOP-1ꢀ

Digital Input Voltage to GND

Operating Temperature Range

Thermal Resistance θ_JA

1ꢀ-Lead SOIC

1.ꢁ mA¹

0.ꢁ mA¹

0 V to V_DD+ 0.3 V

−ꢀ0°C to +10ꢁ°C

1ꢁ8°C/W

73°C/W

16-Lead SOIC

1ꢀ-Lead TSSOP

16-Lead TSSOP

206°C/W

180°C/W

Maximum Junction Temperature (T_Jmax) 1ꢁ0°C

Package Power Dissipation

Storage Temperature Range

Lead Temperature

P_D= (T_Jmax − T_A)/θ_JA

−6ꢁ°C to +1ꢁ0°C

Vapor Phase, 60 sec

Infrared, 1ꢁ sec

21ꢁ°C

220°C

¹Maximum current increases at lower resistance and different packages.

Rev. C | Page 6 of 20

AD5241/AD5242

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

1

2

3

4

5

16

15

14

13

12

A

W

B

14

13

12

11

10

9

A

2

O

A

1

W

2

NC

B

2

W

B

O

2

AD5241

AD5242

O

2

V

DD

SS

TOP VIEW

(Not to Scale)

V

SHDN

DGND

AD1

(Not to Scale)

SS

DD

SHDN

SCL

6

7

8

11 DGND

SCL

SDA

10

8

AD1

AD0

9

AD0

SDA

NC = NO CONNECT

Figure 6. AD5241 Pin Configuration

Figure 7. AD5242 Pin Configuration

Table 4. AD5241 Pin Function Descriptions

Table 5. AD5242 Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

ꢀ

A₁

W₁

B₁

Resistor Terminal A₁.

Wiper Terminal W₁.

Resistor Terminal B₁.

Positive Power Supply, Specified for

Operation from 2.2 V to ꢁ.ꢁ V.

Active low, asynchronous connection of

Wiper W to Terminal B, and open circuit

of Terminal A. RDAC register contents

unchanged. SHDN should tie to V_DD

if not used.

1

2

3

ꢀ

ꢁ

O₁

A₁

W₁

B₁

Logic Output Terminal O₁.

Resistor Terminal A₁.

Wiper Terminal W₁.

Resistor Terminal B₁.

Positive Power Supply, Specified for

Operation from 2.2 V to ꢁ.ꢁ V.

Active Low, Asynchronous Connection

of Wiper W to Terminal B, and Open

Circuit of Terminal A. RDAC register

contents unchanged. SHDN should

tie to V_DD, if not used.

Serial Clock Input.

Serial Data Input/Output.

Programmable Address Bit for Multiple

Package Decoding. Bit AD0 and Bit AD1

provide four possible addresses.

Programmable Address Bit for Multiple

Package Decoding. Bit AD0 and Bit AD1

provide four possible addresses.

Common Ground.

Negative Power Supply, Specified for

Operation from 0 V to −2.7 V.

V_DD

ꢁ

SHDN

6

SHDN

6

7

8

SCL

SDA

AD0

Serial Clock Input.

7

8

9

SCL

SDA

AD0

Serial Data Input/Output.

Programmable Address Bit for Multiple

Package Decoding. Bit AD0 and Bit AD1

provide four possible addresses.

Programmable Address Bit for Multiple

Package Decoding. Bit AD0 and Bit AD1

provide four possible addresses.

Common Ground.

Negative Power Supply, Specified for

Operation from 0 V to −2.7 V.

9

AD1

10

AD1

10

11

DGND

V_SS

11

12

DGND

V_SS

12

13

1ꢀ

O₂

NC

O₁

Logic Output Terminal O₂.

No Connect.

Logic Output Terminal O₁.

13

1ꢀ

1ꢁ

16

O₂

B₂

W₂

A₂

Logic Output Terminal O₂.

Resistor Terminal B₂.

Wiper Terminal W₂.

Resistor Terminal A₂.

Rev. C | Page 7 of 20

AD5241/AD5242

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.50

0.25

0

V

= +2.7V

= +5.5V

= ±2.7V

V

= +2.7V

= +5.5V

= ±2.7V

DD

0.5

V

/V = +2.7V

V

/V = +2.7V/0V

DD SS

0

V

/V = +2.7V/0V, +5.5V/0V

DD SS

–0.5

–1.0

–0.25

–0.50

V

/V = +5.5V/0V, ±2.7V

DD SS

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (Decimal)

Figure 8. RDNL vs. Code

Figure 11. INL vs. Code

1.0

0.5

10k

1k

100

10

1

V

T

= 2.7V

V

= +2.7V

= +5.5V

= ±2.7V

DD

= 25°C

DD

A

V

/V = +2.7V/0V

DD SS

1MΩ

100kΩ

10kΩ

0

V

/V = +5.5V/0V, ±2.7V

DD SS

–0.5

–1.0

0

32

64

96

128

160

192

224

256

–40

–20

0

20

40

60

80

CODE (Decimal)

TEMPERATURE (°C)

Figure 9. RINL vs. Code

Figure 12. Nominal Resistance vs. Temperature

0.25

0.13

0

10k

V

= +2.7V

= +5.5V

= ±2.7V

DD

V

= 5V

DD

1k

100

10

V

/V

=

+2.7V/0V, +5.5V/0V, ±2.7V

DD SS

V

= 3V

DD

–0.13

–0.25

V

= 2.5V

DD

1

0

32

64

96

128

160

192

224

256

0

1

2

3

4

5

CODE (Decimal)

INPUT LOGIC VOLTAGE (V)

Figure 13. Supply Current vs. Input Logic Voltage

Figure 10. DNL vs. Code

Rev. C | Page 8 of 20

AD5241/AD5242

0.1

100

90

80

70

60

50

40

30

20

10

R

V

= 10kΩ

= 5.5V

T

= 25°C

AB

DD

A

V

/V = +2.7V/0V

DD SS

0.01

V

/V = ±2.7V/0V

DD SS

V

/V = +5.5V/0V

DD SS

0.001

–3

–2

–1

0

1

2

3

4

5

6

–20

0

40

TEMPERATURE (°C)

60

80

–40

20

COMMON-MODE (V)

Figure 17. Incremental Wiper Contact vs. V_DD/V_SS

Figure 14. Shutdown Current vs. Temperature

300

70

60

A: V /V = 5.5V/0V

DD SS

CODE = 0xFF

V

/V = 2.7V/0V

= 25°C

DD SS

T

A

B: V /V = 3.3V/0V

DD SS

D

A

10MΩ VERSION

10kΩ VERSION

100kΩ VERSION

250

200

150

100

50

CODE = 0xFF

50

C: V /V = 2.5V/0V

DD SS

CODE = 0xFF

40

D: V /V = 5.5V/0V

DD SS

CODE = 0x55

30

E: V /V = 3.3V/0V

DD SS

CODE = 0x55

20

F: V /V = 2.5V/0V

DD SS

CODE = 0x55

10

E

B

0

–10

–20

–30

F

C

0

10

100

1k

0

32

64

96

128

160

192

224

256

FREQUENCY (kHz)

CODE (Decimal)

Figure 18. Supply Current vs. Frequency

Figure 15. ΔV_WB/ΔT Potentiometer Mode Temperature Coefficient

6

0

120

0xFF

0x80

0x40

V

/V = 2.7V/0V

= 25°C

DD SS

T

100

80

A

100kΩ VERSION

–6

–12

–18

–24

–30

–36

–42

–48

–54

60

0x20

0x10

0x08

0x04

40

20

0

–20

–40

–60

–80

0x02

0x01

10kΩ VERSION

10MΩ VERSION

100

1k

10k

100k

1M

0

32

64

96

128

160

192

224

256

FREQUENCY (Hz)

CODE (Decimal)

Figure 19. AD5242 10 k Ω Gain vs. Frequency vs. Code

Figure 16. ΔR_WB/ΔT Rheostat Mode Temperature Coefficient

Rev. C | Page 9 of 20

AD5241/AD5242

6

0

0xFF

0

0x80

0x40

0x20

0x10

0x08

0x80

0x40

0x20

0x10

0x08

–6

–12

–18

–24

–30

–36

–42

–48

–54

–12

–18

–24

–30

–36

–42

–48

–54

0x04

0x02

0x01

0x04

0x02

0x01

100

1k

10k

100k

100

1k

10k

100k

FREQUENCY (Hz)

Figure 20. AD5242 100 kΩ Gain vs. Frequency vs. Code

Figure 21. AD5242 1 MΩ Gain vs. Frequency vs. Code

Rev. C | Page 10 of 20

AD5241/AD5242

TEST CIRCUITS

Figure 22 to Figure 30 define the test conditions used in the product specifications table.

5V

OP279

V_OUT

DUT

A

V+ = V

DD

V_IN

N

1 LSB = V+/2

W

OFFSET

GND

V+

A

DUT

B

V

MS

OFFSET

BIAS

Figure 22. Potentiometer Divider Nonlinearity Error (INL, DNL)

Figure 27. Noninverting Gain

NO CONNECT

DUT

A

+15V

I

W

DUT

A

V

IN

W

V

OP42

OUT

OFFSET

GND

B

V

MS

2.5V

–15V

Figure 28. Gain vs. Frequency

Figure 23. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

0.1V

R

=

SW

I

SW

CODE = 0x00

DUT

W

I

= V /R

DD NOMINAL

W

A

V

B

W

0.1V

W

I

SW

V

MS2

B

V

R

= [V

MS1

– V ]/I

MS2

MS1

W

TO V

DD

SS

Figure 29. Incremental On Resistance

Figure 24. Wiper Resistance

NC

V

A

V+ = V ±10%

DD

Δ

V_MS

V_DD

I

PSRR (dB) = 20 LOG

V_DD

DUT

CM

A

B

Δ

V

DD

W

A

Δ

V_MS

%

W

V+

PSS (%/%) =

MS

V_SS

Δ

V_DD

GND

V

CM

B

V

NC

Figure 30. Common-Mode Leakage Current

Figure 25. Power Supply Sensitivity (PSS, PSRR)

A

B

DUT

5V

W

OP279

V

OUT

OFFSET

GND

OFFSET

BIAS

Figure 26. Inverting Gain

Rev. C | Page 11 of 20

AD5241/AD5242

THEORY OF OPERATION

The AD5241/AD5242 provide a single-/dual-channel, 256-

position digitally controlled variable resistor (VR) device. The

terms VR, RDAC, and programmable resistor are commonly

used interchangeably to refer to digital potentiometer.

Figure 31 shows a simplified diagram of the equivalent RDAC

circuit where the last resistor string is not accessed; therefore,

there is 1 LSB less of the nominal resistance at full scale in

addition to the wiper resistance.

To program the VR settings, refer to the Digital Interface section.

Both parts have an internal power-on preset that places the wiper

in midscale during power-on that simplifies the fault condition

The general equation determining the digitally programmed

resistance between W and B is

D

256

R

_WB(D) =

× R_AB+ R_W

(1)

SHDN

recovery at power-up. In addition, the shutdown pin (

)

of AD5241/AD5242 places the RDAC in an almost zero power

consumption state where Terminal A is open circuited and Wiper

W is connected to Terminal B, resulting in only leakage current

being consumed in the VR structure. During shutdown, the VR

latch contents are maintained when the RDAC is inactive. When

the part returns from shutdown, the stored VR setting is applied

to the RDAC.

where:

D is the decimal equivalent of the binary code between 0 and 255,

which is loaded in the 8-bit RDAC register.

R

_ABis the nominal end-to-end resistance.

R_Wis the wiper resistance contributed by the on resistance of

the internal switch.

Again, if R_AB= 10 kΩ, Terminal A can be either open circuit or

tied to W. Table 6 shows the R_WBresistance based on the code

set in the RDAC latch.

A

SHDN

SW

SHDN

N

D7

D6

D5

D4

D3

D2

D1

D0

R

SW

2–1

Table 6. R_WB(D) at Selected Codes for R_AB= 10 kΩ

N

2–2

D (DEC)

R_WB(Ω) Output State

SW

2ꢁꢁ

10021

Full-scale (R_WB– 1 LSB + R_W)

128

1

0

ꢁ060

99

60

Midscale

1 LSB

W

SW

R

1

Zero-scale (wiper contact resistance)

RDAC

N

/2

AB

R

LATCH

AND

SW

0

Note that in the zero-scale condition, a finite wiper resistance of

60 Ω is present. Care should be taken to limit the current flow

between W and B in this state to a maximum current of no more

than 20 mA. Otherwise, degradation or possible destruction of

the internal switch contact can occur.

DECODER

DIGITAL CIRCUITRY

OMITTED FOR CLARITY

B

Figure 31. Equivalent RDAC Circuit

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

Similar to the mechanical potentiometer, the resistance of the

RDAC between Wiper W and Terminal A also produces a

digitally controlled resistance, R_WA. When these terminals are

used, Terminal B can be opened or tied to the wiper terminal.

The minimum R_WAresistance is for Data 0xFF and increases as

the data loaded in the latch decreases in value. The general

equation for this operation is

The nominal resistance of the RDAC between Terminal A and

Terminal B is available in 10 kΩ, 100 kΩ, and 1 MΩ. The final two

or three digits of the part number determine the nominal resistance

value, for example, 10 kΩ = 10, 100 kΩ = 100, and 1 MΩ = 1 M.

The nominal resistance (R_AB) of the VR has 256 contact points

accessed by the wiper terminal, plus the B terminal contact. The

8-bit data in the RDAC latch is decoded to select one of the 256

possible settings. Assume a 10 kΩ part is used; the first connection

of the wiper starts at the B terminal for Data 0x00. Because there is

a 60 Ω wiper contact resistance, such connection yields a minimum

of 60 Ω resistance between Terminal W and Terminal B. The

second connection is the first tap point that corresponds to 99 Ω

(R_WB= R_AB/256 + R_W= 39 + 60) for Data 0x01. The third connection

is the next tap point representing 138 Ω (39 × 2 + 60) for Data 0x02,

and so on. Each LSB data value increase moves the wiper up the

resistor ladder until the last tap point is reached at 10,021 Ω

[R_AB– 1 LSB + R_W].

256 − D

256

R

_WA(D) =

× R_AB+ R_W

(2)

For R_AB= 10 kΩ, Terminal B can be either open circuit or tied

to W. Table 7 shows the R_WAresistance based on the code set in

the RDAC latch.

Table 7. R_WA(D) at Selected Codes for R_AB= 10 kΩ

D (DEC)

R_WA(Ω)

Output State

2ꢁꢁ

128

1

99

Full-scale

Midscale

1 LSB

ꢁ060

10021

10060

0

Zero-scale

Rev. C | Page 12 of 20

AD5241/AD5242

The typical distribution of the nominal resistance R_ABfrom

channel to channel matches within 1% for AD5242. Device-

to-device matching is process lot dependent, and it is possible to

have 30% variation. Because the resistance element is processed in

thin film technology, the change in R_ABwith temperature has no

more than a 30 ppm/°C temperature coefficient.

DIGITAL INTERFACE

2-Wire Serial Bus

The AD5241/AD5242 are controlled via an I²C-compatible

serial bus. The RDACs are connected to this bus as slave devices.

Referring to Figure 3 and Figure 4, the first byte of AD5241/

AD5242 is a slave address byte. It has a 7-bit slave address and

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

W

an R/ bit. The five MSBs are 01011 and the following two bits

are determined by the state of the AD0 and AD1 pins of the

device. AD0 and AD1 allow users to use up to four of these

devices on one bus.

The 2-wire, I²C serial bus protocol operates as follows:

The digital potentiometer easily generates output voltages at

wiper-to-B and wiper-to-A to be proportional to the input

voltage at A-to-B. Unlike the polarity of V_DD/V_SS, which must

be positive, voltage across terminal A to terminal B, terminal W

to terminal A, and terminal W to terminal B can be at either

polarity provided that V_SSis powered by a negative supply.

1. The master initiates a data transfer by establishing a start

condition, which is when a high-to-low transition on the SDA

line occurs while SCL is high (see Figure 4). The following

byte is the Frame 1, slave address byte, which consists of the

If ignoring the effect of the wiper resistance for approximation,

connecting Terminal A to 5 V and Terminal B to ground produces

an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less

than 5 V. Each LSB of voltage is equal to the voltage applied across

Terminal AB divided by the 256 positions of the potentiometer

divider. Because AD5241/AD5242 can be supplied by dual

supplies, the general equation defining the output voltage at V_W

with respect to ground for any valid input voltage applied to

Terminal A and Terminal B is

W

7-bit slave address followed by an R/ bit (this bit determines

whether data is read from or written to the slave device).

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is the acknowledge bit). At this stage,

all other devices on the bus remain idle while the selected

device waits for data to be written to or read from its serial

D

256

256 − D

256

W

register. If the R/ bit is high, the master reads from the

V_W

(

D

)

=

V_A+

V_B

(3)

W

slave device. If the R/ bit is low, the master writes to the

slave device.

which can be simplified to

2. A write operation contains an extra instruction byte more

than the read operation. The Frame 2 instruction byte in

write mode follows the slave address byte. The MSB of the

D

256

V_W

(

D

)

=

V_AB+V_B

(4)

where D is the decimal equivalent of the binary code between 0

to 255 that is loaded in the 8-bit RDAC register.

A

instruction byte labeled /B is the RDAC subaddress select. A

low selects RDAC1 and a high selects RDAC2 for the dual-

A

For a more accurate calculation, including the effects of wiper

resistance, V_Wcan be found as

channel AD5242. Set /B to low for the AD5241. The

second MSB, RS, is the midscale reset. A logic high of this

bit moves the wiper of a selected RDAC to the center tap

where R_WA= R_WB. The third MSB, SD, is a shutdown bit. A

logic high on SD causes the RDAC to open circuit at

Terminal A while shorting the wiper to Terminal B. This

operation yields almost a 0 Ω rheostat mode or 0 V in

potentiometer mode. This SD bit serves the same function

R

_WB(D)

R_AB

R

_WA(D)

R_AB

V_W

(

D

)

=

V_A+

V_B

(5)

where R_WB(D) and R_WA(D) can be obtained from Equation 1 and

Equation 2.

Operation of the digital potentiometer in divider mode results

in a more accurate operation over temperature. Unlike rheostat

mode, the output voltage is dependent on the ratio of the internal

resistors, R_WAand R_WB, and not the absolute values; therefore,

the temperature drift reduces to 5 ppm/°C.

SHDN

as the

pin except that the

pin reacts to active

low. The following two bits are O₂and O₁. They are extra

programmable logic outputs that users can use to drive

other digital loads, logic gates, LED drivers, analog switches,

and the like. The three LSBs are don’t care (see Figure 4).

3. After acknowledging the instruction byte, the last byte in

write mode is the, Frame 3 data byte. Data is transmitted

over the serial bus in sequences of nine clock pulses (eight

data bits followed by an acknowledge bit). The transitions

on the SDA line must occur during the low period of SCL

and remain stable during the high period of SCL (see Figure 4).

Rev. C | Page 13 of 20

AD5241/AD5242

4. Unlike the write mode, the data byte follows immediately

after the acknowledgment of the slave address byte in

Frame 2 read mode. Data is transmitted over the serial bus

in sequences of nine clock pulses (slightly different from

the write mode, there are eight data bits followed by a no

acknowledge Logic 1 bit in read mode). Similarly, the

transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of

SCL (see Figure 5).

5. When all data bits have been read or written, a stop condition

is established by the master. A stop condition is defined as

a low-to-high transition on the SDA line while SCL is high.

In write mode, the master pulls the SDA line high during

the tenth clock pulse to establish a stop condition (see

Figure 4). In read mode, the master issues a no acknowledge

for the ninth clock pulse (that is, the SDA line remains high).

The master then brings the SDA line low before the tenth

clock pulse, which goes high to establish a stop condition

(see Figure 5).

MULTIPLE DEVICES ON ONE BUS

Figure 33 shows four AD5242 devices on the same serial bus.

Each has a different slave address because the state of their AD0

and AD1 pins are different. This allows each RDAC within each

device to be written to or read from independently. The master

device output bus line drivers are open-drain pull-downs in a

fully I²C-compatible interface. Note, a device is addressed properly

only if the bit information of AD0 and AD1 in the slave address

byte matches with the logic inputs at the AD0 and AD1 pins of

that particular device.

LEVEL-SHIFT FOR BIDIRECTIONAL INTERFACE

While most old systems can operate at one voltage, a new

component may be optimized at another. When they operate

the same signal at two different voltages, a proper method of

level-shifting is needed. For instance, a 3.3 V E²PROM can be

used to interface with a 5 V digital potentiometer. A level-shift

scheme is needed to enable a bidirectional communication so that

the setting of the digital potentiometer can be stored to and

retrieved from the E²PROM. Figure 32 shows one of the techniques.

M1 and M2 can be N-channel FETs (2N7002) or low threshold

FDV301N if V_DDfalls below 2.5 V.

A repeated write function gives the user flexibility to update the

RDAC output a number of times after addressing and instructing

the part only once. During the write cycle, each data byte updates

the RDAC output. For example, after the RDAC has acknowledged

its slave address and instruction bytes, the RDAC output is

updated. If another byte is written to the RDAC while it is still

addressed to a specific slave device with the same instruction,

this byte updates the output of the selected slave device. If

different instructions are needed, the write mode has to start a

completely new sequence with a new slave address, instruction,

and data bytes transferred again. Similarly, a repeated read

function of the RDAC is also allowed.

V

= 3.3V

V

= 5V

DD

R_P

G

S

D

SDA1

SCL1

SDA2

M1

G

S

D

SCL2

M2

3.3V

5V

AD5242

2

E PROM

Figure 32. Level-Shift for Different Voltage Devices Operation

READBACK RDAC VALUE

Specific to the AD5242 dual-channel device, the channel of

interest is the one that was previously selected in the write mode.

In addition, to read both RDAC values consecutively, users have to

perform two write-read cycles. For example, users may first specify

the RDAC1 subaddress in write mode (it is not necessary to issue

the data byte and stop condition), and then change to read mode

to read the RDAC1 value. To continue reading the RDAC2 value,

users have to switch back to write mode, specify the subaddress,

and then switch once again to read mode to read the RDAC2

value. It is not necessary to issue the write mode data byte or

the first stop condition for this operation. Users should refer to

Figure 4 and Figure 5 for the programming format.

5V

R

P

SDA

SCL

MASTER

V

DD

SDA SCL

AD1

SDA SCL

AD1

SDA SCL

AD1

AD0

AD5242

Figure 33. Multiple AD5242 Devices on One Bus

Rev. C | Page 1ꢀ of 20

AD5241/AD5242

ADDITIONAL PROGRAMMABLE LOGIC OUTPUT

SHUTDOWN FUNCTION

The AD5241/AD5242 feature additional programmable logic

outputs, O₁and O₂, that can be used to drive digital load, analog

switches, and logic gates. They can also be used as a self-contained

shutdown preset to Logic 0 that is further explained in the

Shutdown Function section. O₁and O₂default to Logic 0 during

power-up. The logic states of O₁and O₂can be programmed in

Frame 2 under the write mode (see Figure 4). Figure 34 shows

the output stage of O₁, which employs large P-channel and N-

channel MOSFETs in push-pull configuration. As shown in

Figure 34, the output is equal to V_DDor V_SS, and these logic

outputs have adequate current driving capability to drive

milliamperes of load.

SHDN

pin or

Shutdown can be activated by strobing the

programming the SD bit in the write mode instruction byte (see

Table 2). If the RDAC Register 1 or RDAC Register 2 (AD5242

only) is placed in shutdown mode by the software, SD bit, the

part returns the wiper to its prior position when a new command

is received.

In addition, shutdown can be implemented with the device digital

output, as shown in Figure 35. In this configuration, the device

is shutdown during power-up but users are allowed to program

the device. Thus, when O₁is programmed high, the device exits

shutdown mode and responds to the new setting. This self-contained

shutdown function allows absolute shutdown during power-up,

which is crucial in hazardous environments, and it does not add

extra components.

V

DD

M

P

1

2

O

1

IN

O

1

SHDN

O

DATA IN FRAME 2

M

1

N

R

PD

OF WRITE MODE

V

SS

Figure 34. Output Stage of Logic Output, O₁

SDA

SCL

Users can also activate O₁and O₂in the following three different

ways without affecting the wiper settings:

Figure 35. Shutdown by Internal Logic Output, O₁

340Ω

LOGIC

1. Start, slave address byte, acknowledge, instruction byte

with O₁and O₂specified, acknowledge, stop.

2. Complete the write cycle with stop, then start, slave address

byte, acknowledge, instruction byte with O₁and O₂specified,

acknowledge, stop.

V

SS

Figure 36. ESD Protection of Digital Pins

3. Do not complete the write cycle by not issuing the stop,

then start, slave address byte, acknowledge, instruction

byte with O₁and O₂specified, acknowledge, stop.

A,B,W

V

SS

All digital inputs are protected with a series input resistor and

the parallel Zener ESD structures shown in Figure 36. This

Figure 37. ESD Protection of Resistor Terminals

SHDN

applies to the digital input pins, SDA, SCL, and

.

Rev. C | Page 1ꢁ of 20

AD5241/AD5242

OUTLINE DIMENSIONS

5.10

5.00

4.90

14

8

7

4.50

4.40

4.30

6.40

BSC

1

PIN 1

0.65 BSC

1.05

1.00

0.80

1.20

MAX

0.20

0.09

0.75

0.60

0.45

8°

0°

0.15

0.05

COPLANARITY

0.10

SEATING

PLANE

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 38. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

8.75 (0.3445)

8.55 (0.3366)

8

7

14

1

6.20 (0.2441)

5.80 (0.2283)

4.00 (0.1575)

3.80 (0.1496)

1.27 (0.0500)

0.50 (0.0197)

0.25 (0.0098)

45°

BSC

1.75 (0.0689)

1.35 (0.0531)

0.25 (0.0098)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

1.27 (0.0500)

0.40 (0.0157)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 39. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-14)

Dimensions shown in millimeters and (inches)

Rev. C | Page 16 of 20

AD5241/AD5242

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

10.00 (0.3937)

9.80 (0.3858)

9

8

16

1

6.20 (0.2441)

5.80 (0.2283)

4.00 (0.1575)

3.80 (0.1496)

1.27 (0.0500)

0.50 (0.0197)

0.25 (0.0098)

45°

BSC

1.75 (0.0689)

1.35 (0.0531)

0.25 (0.0098)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

1.27 (0.0500)

0.40 (0.0157)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 41. 16-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-16)

Dimensions shown in millimeters and (inches)

Rev. C | Page 17 of 20

AD5241/AD5242

ORDERING GUIDE

Model^{1, 2}

No. of Channels End-to-End R_AB

Temperature Range

Package Description Package Option

ADꢁ2ꢀ1BR10

1

10 kΩ

100 kΩ

1 MΩ

–ꢀ0°C to +10ꢁ°C

1ꢀ-Lead SOIC_N

1ꢀ-Lead TSSOP

1ꢀ-Lead SOIC_N

1ꢀ-Lead TSSOP

1ꢀ-Lead SOIC_N

1ꢀ-Lead TSSOP

R-1ꢀ

ADꢁ2ꢀ1BR10-REEL7

ADꢁ2ꢀ1BRZ10

R-1ꢀ

ADꢁ2ꢀ1BRZ10-RL7

ADꢁ2ꢀ1BRU10

ADꢁ2ꢀ1BRU10-REEL7

ADꢁ2ꢀ1BRUZ10

ADꢁ2ꢀ1BRUZ10-R7

ADꢁ2ꢀ1BR100

ADꢁ2ꢀ1BR100-REEL7

ADꢁ2ꢀ1BRZ100

ADꢁ2ꢀ1BRZ100-RL7

ADꢁ2ꢀ1BRU100

ADꢁ2ꢀ1BRU100-REEL7

ADꢁ2ꢀ1BRUZ100

ADꢁ2ꢀ1BRUZ100-R7

ADꢁ2ꢀ1BR1M

ADꢁ2ꢀ1BRZ1M

ADꢁ2ꢀ1BRZ1M-REEL

ADꢁ2ꢀ1BRU1M

R-1ꢀ

RU-1ꢀ

R-1ꢀ

RU-1ꢀ

R-1ꢀ

1 MΩ

ADꢁ2ꢀ1BRU1M-REEL7

ADꢁ2ꢀ1BRUZ1M

ADꢁ2ꢀ1BRUZ1M-R7

RU-1ꢀ

ADꢁ2ꢀ2BR10

2

10 kΩ

–ꢀ0°C to +10ꢁ°C

16-Lead SOIC_N

16-Lead TSSOP

16-Lead SOIC_N

16-Lead TSSOP

16-Lead SOIC_N

16-Lead TSSOP

R-16

ADꢁ2ꢀ2BR10-REEL7

ADꢁ2ꢀ2BRZ10

10 kΩ

R-16

10 kΩ

R-16

ADꢁ2ꢀ2BRZ10-REEL7

ADꢁ2ꢀ2BRU10

ADꢁ2ꢀ2BRU10-REEL7

ADꢁ2ꢀ2BRUZ10

ADꢁ2ꢀ2BRUZ10-RL7

ADꢁ2ꢀ2BR100

ADꢁ2ꢀ2BR100-REEL7

ADꢁ2ꢀ2BRZ100

ADꢁ2ꢀ2BRZ100-REEL7

ADꢁ2ꢀ2BRU100

ADꢁ2ꢀ2BRU100-REEL7

ADꢁ2ꢀ2BRUZ100

ADꢁ2ꢀ2BRUZ100-RL7

ADꢁ2ꢀ2BR1M

ADꢁ2ꢀ2BRZ1M

ADꢁ2ꢀ2BRU1M

ADꢁ2ꢀ2BRU1M-REEL7

ADꢁ2ꢀ2BRUZ1M

ADꢁ2ꢀ2BRUZ1M-REEL7

EVAL-ADꢁ2ꢀ2EBZ

10 kΩ

R-16

RU-16

R-16

RU-16

R-16

RU-16

10 kΩ

100 kΩ

1 MΩ

Evaluation Board

¹The ADꢁ2ꢀ1/ADꢁ2ꢀ2 die size is 69 mil × 78 mil, ꢁ,382 sq. mil. Contains 386 transistors for each channel. Patent Number ꢁ,ꢀ9ꢁ,2ꢀꢁ applies.

²Z = RoHS Compliant Part.

Rev. C | Page 18 of 20

AD5241/AD5242

NOTES

Rev. C | Page 19 of 20

AD5241/AD5242

NOTES

registered trademarks are the property of their respective owners.

D00926-0-12/09(C)

Rev. C | Page 20 of 20

型号:	AD5241BRU10
Source Url Status Check Date：	2013-05-01 14:56:10.99
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	ANALOG DEVICES INC
零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP14,.25
针数：	14
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	7.47
其他特性：	IT CAN ALSO OPERATE FROM A 3V NOM SINGLE SUPPLY OR +/-2.3V TO +/-2.7V DUAL SUPPLY
标称带宽：	0.65 kHz
控制接口：	2-WIRE SERIAL
转换器类型：	DIGITAL POTENTIOMETER
JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e0
长度：	5 mm
湿度敏感等级：	1
标称负供电电压：	-2.5 V
功能数量：	1
位置数：	256
端子数量：	14
最高工作温度：	105 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP14,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	240
电源：	3/5 V
认证状态：	Not Qualified
电阻定律：	LINEAR
最大电阻容差：	30%
最大电阻器端电压：	5.5 V
最小电阻器端电压：	-2.3 V
座面最大高度：	1.2 mm
子类别：	Digital Potentiometers
标称供电电压：	2.5 V
表面贴装：	YES
技术：	CMOS
标称温度系数：	30 ppm/ °C
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
标称总电阻：	10000 Ω
宽度：	4.4 mm
Base Number Matches：	1

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