AD5764CSUZ原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

Complete Quad, 16-Bit, High Accuracy,

Serial Input, Bipolar Voltage Output DAC

Data Sheet

AD5764

FEATURES

GENERAꢀ DESCRIPTION

Complete quad, 16-bit digital-to-analog

converter (DAC)

Programmable output range

10 V, 10.2564 V, or 10.5263 V

The AD5764 is a quad, 16-bit, serial input, bipolar voltage

output DAC that operates from supply voltages of 11.4 V to

16.5 V. Nominal full-scale output range is 1ꢀ V. The AD5764

provides integrated output amplifiers, reference buffers, and

1 ꢀSB maximum INꢀ error, 1 ꢀSB maximum DNꢀ error

ꢀow noise: 60 nV/√Hz

Settling time: 10 μs maximum

proprietary power-up/power-down control circuitry. The part

also features a digital I/O port that is programmed via the serial

interface. The part incorporates digital offset and gain adjust

registers per channel.

Integrated reference buffers

Output control during power-up/brownout

Programmable short-circuit protection

Simultaneous updating via ꢀDAC

The AD5764 is a high performance converter that offers guar-

anteed monotonicity, integral nonlinearity (INL) of 1 LꢁB, low

noise, and 1ꢀ μs settling time. During power-up (when the

supply voltages are changing), VOUTx is clamped to ꢀ V via a

low impedance path.

CꢀR

Asynchronous

to zero code

Digital offset and gain adjust

ꢀogic output control pins

The AD5764 uses a serial interface that operates at clock rates of

up to 3ꢀ MHz and is compatible with DꢁP and microcontroller

interface standards. Double buffering allows the simultaneous

updating of all DACs. The input coding is programmable to

either twos complement or offset binary formats. The asynchro-

nous clear function clears the data register to either bipolar zero or

zero scale depending on the coding used. The AD5764 is ideal

for both closed-loop servo control and open-loop control appli-

cations. The AD5764 is available in a 32-lead TQFP, and offers

guaranteed specifications over the −4ꢀ°C to +85°C industrial

temperature range. ꢁee Figure 1 for the functional block diagram.

DSP-/microcontroller-compatible serial interface

Temperature range: −40°C to +85°C

iCMOS process technology¹

APPꢀICATIONS

Industrial automation

Open-loop/closed-loop servo control

Process control

Data acquisition systems

Automatic test equipment

Automotive test and measurement

High accuracy instrumentation

Table 1. Related Devices

Part No.

AD5764R

AD5744R

Description

AD5764 with internal voltage reference

Complete quad, 14-bit, high accuracy, serial

input, bipolar voltage output DAC with

internal voltage reference

¹For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS® is a technology

platform that enables the development of analog ICs capable of 30 V and operating at 15 V supplies, allowing dramatic reductions in power consumption and package

size, and increased ac and dc performance.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

rights of third parties that may result from its use. Specifications subject to change without notice. No

Tel: 781.329.4700

www.analog.com

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

AD5764

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Function Register ....................................................................... 21

Data Register............................................................................... 21

Coarse Gain Register ................................................................. 21

Fine Gain Register...................................................................... 22

Offset Register ............................................................................ 22

Offset and Gain Adjustment Worked Example...................... 23

Design Features............................................................................... 24

Analog Output Control ............................................................. 24

Digital Offset and Gain Control............................................... 24

Programmable ꢁhort-Circuit Protection ................................ 24

Digital I/O Port........................................................................... 24

Local Ground Offset Adjust...................................................... 24

Applications Information.............................................................. 25

Typical Operating Circuit ......................................................... 25

Layout Guidelines........................................................................... 27

Galvanically Isolated Interface ................................................. 27

Microprocessor Interfacing....................................................... 27

Evaluation Board........................................................................ 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

ꢁpecifications..................................................................................... 4

AC Performance Characteristics................................................ 5

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings............................................................ 9

EꢁD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 1ꢀ

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 17

Theory of Operation ...................................................................... 18

DAC Architecture....................................................................... 18

Reference Buffers........................................................................ 18

ꢁerial Interface ............................................................................ 18

LDAC

ꢁimultaneous Updating via

........................................... 19

Transfer Function....................................................................... 2ꢀ

CLR

Asynchronous Clear (

)....................................................... 2ꢀ

REVISION HISTORY

9/11—Rev. E to Rev. F

Changed 3ꢀ MHz to 5ꢀ MHz Throughout.................................... 1

Changes to t₁, t₂, and t₃Parameters, Table 4.................................. 6

Changes to Table 2ꢀ ....................................................................... 26

Deleted AD5764 to MC68HC11 Interface ꢁection.................... 27

Deleted Figure 38; Renumbered ꢁequentially ............................ 27

Deleted AD5764 to 8XC51 Interface ꢁection, Figure 39,

AD5764 to ADꢁP-21ꢀ1 Interface ꢁection, Figure 4ꢀ, and

AD5764 to PIC16C6x/PIC16C7x Interface ꢁection.................. 28

7/11—Rev. D to Rev. E

Changed 3ꢀ MHz to 5ꢀ MHz Throughout.................................... 1

Changes to t₁, t₂, and t₃Parameters, Table 4.................................. 6

04/08—Rev. A to Rev. B

8/09—Rev. C to Rev. D

Changes to Table ꢁummary ꢁtatement, ꢁpecifications ꢁection...4

Changes to Power Requirements Parameter, Table 2 and

Table ꢁummary ꢁtatement................................................................5

Changes to t₁₆Parameter, Table 4 ....................................................6

Changes to Table 6.......................................................................... 1ꢀ

Changed V_ꢁꢁ/V_DDto AV_ꢁꢁ/AV_DDin Typical Performance

Characteristics ꢁection .................................................................. 13

Changes to Table 16 ....................................................................... 22

Changes to Table 18 ....................................................................... 23

Changes to Typical Operating Circuit ꢁection........................... 28

Changes to AD5764 to ADꢁP-21ꢀ1 ꢁection ............................... 29

Changes to Ordering Guide.......................................................... 3ꢀ

Changes to Table 2 and Table 3 Endnotes ..................................... 6

Changes to t₆Parameter and Endnotes, Table 4........................... 7

1/09—Rev. B to Rev. C

Changes to General Description ꢁection ...................................... 1

Changes to Figure 1.......................................................................... 3

Changes to Table 2 Conditions....................................................... 4

Changes to Table 3 Conditions....................................................... 5

Changes to Table 4 Conditions....................................................... 6

Changes to Figure 5.......................................................................... 8

Changes to Table 5............................................................................ 9

Changes to Table 6.......................................................................... 1ꢀ

Changes to Figure 34...................................................................... 19

Changes to Table 7 and Table 1ꢀ................................................... 2ꢀ

Added Table 8; Renumbered ꢁequentially .................................. 2ꢀ

Changes to Table 11 and Table 12 ................................................ 21

Changes to Digital Offset and Gain Control ꢁection ................ 24

1/07—Rev. 0 to Rev. A

Changes to Absolute Maximum Ratings..................................... 1ꢀ

Changes to Figure 25 and Figure 26............................................. 16

3/06—Revision 0: Initial Version

Rev. F | Page 2 of 28

Data Sheet

AD5764

FUNCTIONAL BLOCK DIAGRAM

AV

SS

RSTOUT

RSTIN

PGND

REFGND

REFAB

DD

SS

DD

VOLTAGE

MONITOR

AND

DV

CC

REFERENCE

BUFFERS

AD5764

CONTROL

DGND

ISCC

16

G1

INPUT

REG A

DATA

REG A

DAC A

DAC B

DAC C

DAC D

SDIN

SCLK

SYNC

SDO

VOUTA

AGNDA

INPUT

SHIFT

G2

REGISTER

AND

GAIN REG A

CONTROL

LOGIC

OFFSET REG A

16

INPUT

REG B

DATA

REG B

VOUTB

AGNDB

G2

GAIN REG B

OFFSET REG B

D0

D1

INPUT

REG C

DATA

REG C

VOUTC

AGNDC

GAIN REG C

OFFSET REG C

BIN/2sCOMP

INPUT

REG D

DATA

REG D

VOUTD

AGNDD

GAIN REG D

CLR

OFFSET REG D

REFERENCE

BUFFERS

LDAC

REFCD

Figure 1.

Rev. F | Page 3 of 28

AD5764

Data Sheet

SPECIFICATIONS

AV_DD= 11.4 V to 16.5 V, AV_ꢁꢁ= −11.4 V to −16.5 V, AGNDx = DGND = REFGND = PGND = ꢀ V; REFAB = REFCD = 5 V;

DV_CC= 2.7 V to 5.25 V, R_LOAD= 1ꢀ kΩ, C_L= 2ꢀꢀ pF. Temperature range: −4ꢀ°C to +85°C; typical at +25°C. Device functionality is

guaranteed to +1ꢀ5°C with degraded performance. All specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter

A Grade

B Grade

C Grade

Unit

Test Conditions/Comments

ACCURACY

Outputs unloaded

Resolution

16

4

1

16

2

1

16

1

Bits

Relative Accuracy (INL)

Differential Nonlinearity

Bipolar Zero Error

LSB max

mV max

Guaranteed monotonic

At 25°C; error at other temperatures

obtained using bipolar zero TC

2

Bipolar Zero Temperature

Coefficient (TC)¹

Zero-Scale Error

2

ppm FSR/°C max

mV max

At 25°C; error at other temperatures

obtained using zero-scale TC

Zero-Scale TC¹

Gain Error

2

0.02

2

0.02

2

0.02

ppm FSR/°C max

% FSR max

At 25°C; error at other temperatures

obtained using gain TC

Gain TC¹

DC Crosstalk¹

2

0.5

2

0.5

2

0.5

ppm FSR/°C max

LSB max

REFERENCE INPUT¹

Reference Input Voltage

DC Input Impedance

Input Current

5

1

5

1

5

1

V nom

MΩ min

μA max

1% for specified performance

Typically 100 MΩ

Typically 30 nA

10

Reference Range

1 to 7

V min to V max

OUTPUT CHARACTERISTICS¹

Output Voltage Range²

10.5263

14

10.5263

14

10.5263

14

V min to V max

AV_DD/AV_SS

=

11.4 V, V_REFIN= 5 V

16.5 V, V_REFIN= 7 V

Output Voltage Drift vs. Time

13

ppm FSR/

500 hours typ

15

ppm FSR/

1000 hours typ

Short-Circuit Current

Load Current

10

1

10

1

10

1

mA typ

mA max

R_ISCC= 6 kΩ, see Figure 31

For specified performance

Capacitive Load Stability

R_LOAD= ∞

R_LOAD= 10 kΩ

DC Output Impedance

DIGITAL INPUTS

200

1000

0.3

200

1000

0.3

200

1000

0.3

pF max

Ω max

DV_CC= 2.7 V to 5.25 V, JEDEC compliant

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input Current

2

0.8

1

2

0.8

1

2

0.8

1

V min

V max

μA max

pF max

Per pin

Pin Capacitance

10

Rev. F | Page 4 of 28

Data Sheet

AD5764

Parameter

DIGITAL OUTPUTS (D0, D1, SDO)¹

A Grade

B Grade

C Grade

Unit

Test Conditions/Comments

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

High Impedance Leakage Current

High Impedance Output

Capacitance

0.4

DV_CC− 1

0.4

DV_CC− 0.5 DV_CC− 0.5

1

0.4

DV_CC− 1

0.4

DV_CC− 1

0.4

DV_CC− 0.5

1

5

V max

V min

V max

V min

μA max

pF typ

DV_CC= 5 V 5%, sinking 200 μA

DV_CC= 5 V 5%, sourcing 200 μA

DV_CC= 2.7 V to 3.6 V, sinking 200 μA

DV_CC= 2.7 V to 3.6 V, sourcing 200 μA

SDO only

1

5

SDO only

POWER REQUIREMENTS

AV_DD/AV_SS

11.4 to

16.5

11.4 to

16.5

11.4 to

16.5

V min to V max

DV_CC

2.7 to 5.25 2.7 to 5.25

2.7 to 5.25 V min to V max

Power Supply Sensitivity¹

∆V_OUT/∆ΑV_DD

AI_DD

AI_SS

DI_CC

−85

3.5

2.75

1.2

−85

3.5

2.75

1.2

−85

3.5

2.75

1.2

dB typ

mA/channel max

mA max

Outputs unloaded

V_IH= DV_CC, V_IL= DGND, 750 μA typical

12 V operation output unloaded

Power Dissipation

275

mW typ

¹Guaranteed by design and characterization; not production tested.

²Output amplifier headroom requirement is 1.4 V minimum.

AC PERFORMANCE CHARACTERISTICS

AV_DD= 11.4 V to 16.5 V, AV_ꢁꢁ= −11.4 V to −16.5 V, AGNDx = DGND = REFGND = PGND = ꢀ V; REFAB = REFCD = 5 V;

DV_CC= 2.7 V to 5.25 V, R_LOAD= 1ꢀ kΩ, C_L= 2ꢀꢀ pF. All specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter

A Grade B Grade C Grade Unit

Test Conditions/Comments

Full-scale step to 1 LSB

512 LSB step settling

DYNAMIC PERFORMANCE¹

Output Voltage Settling Time

8

μs typ

10

2

10

2

10

2

μs max

μs typ

Slew Rate

5

8

25

80

8

5

8

25

80

8

5

8

25

80

8

V/μs typ

nV-sec typ

mV max

dB typ

nV-sec typ

Digital-to-Analog Glitch Energy

Glitch Impulse Peak Amplitude

Channel-to-Channel Isolation

DAC-to-DAC Crosstalk

Digital Crosstalk

2

Digital Feedthrough

Effect of input bus activity on DAC

outputs

Output Noise (0.1 Hz to 10 Hz)

Output Noise (0.1 Hz to 100 kHz)

1/f Corner Frequency

0.1

45

1

0.1

45

1

0.1

45

1

LSB p-p typ

μV rms max

kHz typ

Output Noise Spectral Density

Complete System Output Noise Spectral

Density²

60

80

60

80

60

80

nV/√Hz typ

Measured at 10 kHz

¹Guaranteed by design and characterization; not production tested.

²Includes noise contributions from integrated reference buffers, 16-bit DAC, and output amplifier.

Rev. F | Page 5 of 28

AD5764

Data Sheet

TIMING CHARACTERISTICS

AV_DD= 11.4 V to 16.5 V, AV_ꢁꢁ= −11.4 V to −16.5 V, AGNDx = DGND = REFGND = PGND = ꢀ V; REFAB = REFCD = 5 V;

DV_CC= 2.7 V to 5.25 V, R_LOAD= 1ꢀ kΩ, C_L= 2ꢀꢀ pF. All specifications T_MINto T_MAX, unless otherwise noted.

Table 4.

Parameter^{1, 2, 3}

ꢀimit at T_MIN, T_MAX

Unit

Description

t₁

t₂

t₃

t₄

33

13

90

2

ns min

μs min

ns min

ns max

μs max

ns min

μs max

ns max

ns min

μs max

ns min

SCLK cycle time

SCLK high time

SCLK low time

SYNC falling edge to SCLK falling edge setup time

24^thSCLK falling edge to SYNC rising edge

Minimum SYNC high time

4

t₅

t₆

t₇

t₈

t₉

Data setup time

Data hold time

SYNC rising edge to LDAC falling edge (all DACs updated)

SYNC rising edge to LDAC falling edge (single DAC updated)

LDAC pulse width low

5

1.7

480

10

500

10

2

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

LDAC falling edge to DAC output response time

DAC output settling time

CLR pulse width low

CLR pulse activation time

5, 6

t₁₅

25

13

2

SCLK rising edge to SDO valid

SYNC rising edge to SCLK falling edge

SYNC rising edge to DAC output response time (LDAC = 0)

LDAC falling edge to SYNC rising edge

t₁₆

t₁₇

t₁₈

170

¹Guaranteed by design and characterization; not production tested.

²All input signals are specified with t_R= t_F= 5 ns (10% to 90% of DV_CC) and timed from a voltage level of 1.2 V.

³See Figure 2, Figure 3, and Figure 4.

⁴Standalone mode only.

⁵Measured with the load circuit of Figure 5.

⁶Daisy-chain mode only.

Rev. F | Page 6 of 28

Data Sheet

AD5764

Timing Diagrams

t₁

SCLK

SYNC

1

2

24

t₃

t₂

t₆

t₄

t₅

t₈

t₇

DB23

SDIN

DB0

t₁₀

t₉

LDAC

t₁₈

t₁₂

t₁₁

VOUTx

LDAC = 0

t₁₂

t₁₇

VOUTx

CLR

t₁₃

t₁₄

VOUTx

Figure 2. Serial Interface Timing Diagram

t₁

SCLK

24

48

t₃

t₂

t₆

t₅

t₁₆

t₄

SYNC

SDIN

t₈

t₇

DB23

DB0

DB23

DB0

INPUT WORD FOR DAC N

INPUT WORD FOR DAC N–1

INPUT WORD FOR DAC N

t₁₅

DB23

DB0

SDO

t₉

UNDEFINED

t₁₀

LDAC

Figure 3. Daisy-Chain Timing Diagram

Rev. F | Page 7 of 28

AD5764

Data Sheet

SCLK

24

48

SYNC

SDIN

DB23

DB0

DB23

DB0

NOP CONDITION

INPUT WORD SPECIFIES

REGISTER TO BE READ

DB23

DB0

SDO

UNDEFINED

SELECTED REGISTER DATA

CLOCKED OUT

Figure 4. Readback Timing Diagram

200µA

I

OL

V

(MIN) OR

(MAX)

TO SDO

OH

OL

C

L

50pF

200µA

I

OH

Figure 5. Load Circuit for SDO Timing Diagram

Rev. F | Page 8 of 28

Data Sheet

AD5764

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted. Transient currents of up to

1ꢀꢀ mA do not cause ꢁCR latch-up.

ꢁtresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 5.

Parameter

Rating

AV_DDto AGNDx, DGND

AV_SSto AGNDx, DGND

DV_CCto DGND

−0.3 V to +17 V

+0.3 V to −17 V

−0.3 V to +7 V

Digital Inputs to DGND

−0.3 V to DV_CC+ 0.3 V or 7 V

(whichever is less)

ESD CAUTION

Digital Outputs to DGND

REFAB, REFCD to AGNDx, PGND

VOUTA, VOUTB, VOUTC, VOUTD to

AGNDx

−0.3 V to DV_CC+ 0.3 V

−0.3 V to AV_DD+ 0.3 V

AV_SSto AV_DD

AGNDx to DGND

−0.3 V to +0.3 V

Operating Temperature Range

Industrial

Storage Temperature Range

Junction Temperature (T_Jmax)

32-Lead TQFP

−40°C to +85°C

−65°C to +150°C

150°C

θ_JAThermal Impedance

θ_JCThermal Impedance

Lead Temperature

65°C/W

12°C/W

JEDEC industry standard

J-STD-020

Soldering

Rev. F | Page 9 of 28

AD5764

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

24

AGNDA

23 VOUTA

22

SYNC

PIN 1

SCLK

SDIN

SDO

VOUTB

AD5764

TOP VIEW

(Not to Scale)

21 AGNDB

20 AGNDC

19 VOUTC

18 VOUTD

CLR

LDAC

D0

AGNDD

17

D1

9

10 11 12 13 14 15 16

NC = NO CONNECT

Figure 6. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

SYNC

Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low,

data is transferred in on the falling edge of SCLK.

2

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This

operates at clock speeds up to 30 MHz.

3

4

5

SDIN

SDO

CLR

Serial Data Input. Data must be valid on the falling edge of SCLK.

Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode.

Negative Edge Triggered Input. Asserting this pin sets the data register to 0x0000. There is an internal

pull-up device on this logic input. Therefore, this pin can be left floating and defaults to a Logic 1

condition.

6

LDAC

Load DAC. Logic input. This is used to update the data register and consequently the analog outputs.

When tied permanently low, the addressed data register is updated on the rising edge of SYNC. If

LDAC is held high during the write cycle, the DAC input shift register is updated but the output

update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated

simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected.

7, 8

D0, D1

Digital I/O Port. The user can set up these pins as inputs or outputs that are configurable and readable

over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DV_CC.

When programmed as outputs, D0 and D1 are referenced by DV_CCand DGND.

9

RSTOUT

RSTIN

Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If

desired, it can be used to control other system components.

Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to

this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1.

Register values remain unchanged.

10

11

12

13, 31

14

15, 30

16

DGND

DV_CC

AV_DD

PGND

AV_SS

Digital Ground.

Digital Supply. Voltage ranges from 2.7 V to 5.25 V.

Positive Analog Supply. Voltage ranges from 11.4 V to 16.5 V.

Ground Reference Point for Analog Circuitry.

Negative Analog Supply. Voltage ranges from −11.4 V to −16.5 V.

Resistor Connection for Pin Programmable Short-Circuit Current. This pin is used in association with an

optional external resistor to AGND to program the short-circuit current of the output amplifiers. Refer

to the Design Features section for further details.

ISCC

17

18

AGNDD

VOUTD

Ground Reference Pin for DAC D Output Amplifier.

Analog Output Voltage of DAC D. This pin is a buffered output with a nominal full-scale output range

of 10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load.

19

20

VOUTC

AGNDC

Analog Output Voltage of DAC C. This pin is a buffered output with a nominal full-scale output range

of 10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load.

Ground Reference Pin for DAC C Output Amplifier.

Rev. F | Page 10 of 28

Data Sheet

AD5764

Pin No.

21

22

Mnemonic

Description

AGNDB

VOUTB

Ground Reference Pin for DAC B Output Amplifier.

Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of 10 V.

The output amplifier is capable of directly driving a 10 kΩ, 200 pF load.

23

VOUTA

Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of 10 V.

The output amplifier is capable of directly driving a 10 kΩ, 200 pF load.

24

25

AGNDA

REFAB

Ground Reference Pin for DAC A Output Amplifier.

External Reference Voltage Input for Channel A and Channel B. Reference input range is 1 V to 7 V;

programs the full-scale output voltage. V_REFIN= 5 V for specified performance.

26

REFCD

External Reference Voltage Input for Channel C and Channel D. Reference input range is 1 V to 7 V;

programs the full-scale output voltage. V_REFIN= 5 V for specified performance.

27, 29

28

32

NC

No Connect.

REFGND

BIN/2sCOMP

Reference Ground Return for the Reference Generator and Buffers.

Determines the DAC Coding. This pin should be hardwired to either DV_CCor DGND. When hardwired to

DV_CC, input coding is offset binary. When hardwired to DGND, input coding is twos complement

(see Table 7 and Table 8).

Rev. F | Page 11 of 28

AD5764

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

T

= 25°C

T

= 25°C

A

AV /AV = ±15V

AV /AV = ±12V

DD SS

0.8

DD

SS

V

= 5V

V

= 5V

REFIN

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

10000

20000

30000

40000

50000

60000

0

10000

20000

30000

40000

50000

60000

DAC CODE

Figure 7. Integral Nonlinearity Error vs. Code,

Figure 10. Differential Nonlinearity Error vs. Code,

AV_DD/AV_SS

=

15 V

AV_DD/AV_SS

=

12 V

1.0

0.8

0.5

0.4

0.3

0.2

0.1

0

T

= 25°C

T = 25°C

A

AV /AV = ±15V

DD SS

A

AV /AV = ±12V

DD

SS

V

= 5V

V

= 5V

REFIN

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.1

–0.2

–40

10000

20000

30000

40000

50000

60000

–20

0

20

40

60

80

100

DAC CODE

TEMPERATURE (°C)

Figure 8. Integral Nonlinearity Error vs. Code,

AV_DD/AV_SS12 V

Figure 11. Integral Nonlinearity Error vs. Temperature,

AV_DD/AV_SS15 V

=

1.0

0.8

0.5

0.4

0.3

0.2

0.1

0

T

= 25°C

A

T

= 25°C

A

AV /AV = ±15V

DD

SS

AV /AV = ±12V

DD

SS

= 5V

V

= 5V

REFIN

V

REFIN

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.1

–40

10000

20000

30000

40000

50000

60000

–20

0

20

40

60

80

100

DAC CODE

TEMPERATURE (°C)

Figure 9. Differential Nonlinearity Error vs. Code,

AV_DD/AV_SS15 V

Figure 12. Integral Nonlinearity Error vs. Temperature,

AV_DD/AV_SS12 V

=

Rev. F | Page 12 of 28

Data Sheet

AD5764

0.15

0.10

T

V

= 25°C

A

= 5V

REFIN

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.05

–0.10

–0.15

–0.20

–0.25

T

= 25°C

A

AV /AV = ±15V

V

DD

SS

= 5V

REFIN

–40

–20

0

20

40

60

80

100

11.4

12.4

13.4

14.4

15.4

16.4

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

Figure 13. Differential Nonlinearity Error vs. Temperature,

AV_DD/AV_SS15 V

Figure 16. Differential Nonlinearity Error vs. Supply Voltage

=

0.8

0.15

0.10

T

= 25°C

A

AV /AV = ±16.5V

DD SS

0.6

0.4

0.05

0.2

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.2

–0.4

–0.6

–0.8

–1.0

T

= 25°C

A

AV /AV = ±12V

V

DD

SS

= 5V

REFIN

1

2

3

4

5

6

7

–40

–20

0

20

40

60

80

100

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

Figure 17. Integral Nonlinearity Error vs. Reference Voltage,

Figure 14. Differential Nonlinearity Error vs. Temperature,

AV_DD/AV_SS

= 16.5 V

AV_DD/AV_SS

=

12 V

0.4

0.3

0.5

0.4

0.3

0.2

0.1

0

T

= 25°C

T

V

= 25°C

A

AV /AV = ±16.5V

= 5V

DD SS

REFIN

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.1

–0.2

11.4

1

2

3

4

5

6

7

12.4

13.4

14.4

15.4

16.4

REFERENCE VOLTAGE (V)

SUPPLY VOLTAGE (V)

Figure 18. Differential Nonlinearity Error vs. Reference Voltage,

AV_DD/AV_SS16.5 V

Figure 15. Integral Nonlinearity Error vs. Supply Voltage

=

Rev. F | Page 13 of 28

AD5764

Data Sheet

0.6

T

0.8

0.6

0.4

0.2

0

= 25°C

A

V

= 5V

REFIN

AV /AV = ±15V

DD SS

AV /AV = ±16.5V

0.4

DD

SS

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

AV /AV = ±12V

DD SS

–0.2

–0.4

1

2

3

4

5

6

7

–40

–20

0

20

40

60

80

100

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

Figure 19. Total Unadjusted Error vs. Reference Voltage,

Figure 22. Bipolar Zero Error vs. Temperature

AV_DD/AV_SS

=

16.5 V

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

14

13

12

11

10

9

V

= 5V

REFIN

T

V

= 25°C

A

= 5V

REFIN

|I

DD

|

AV /AV = ±12V

DD SS

AV /AV = ±15V

DD SS

|I

SS

|

–0.2

–40

8

11.4

–20

0

20

40

60

80

100

12.4

13.4

14.4

15.4

16.4

TEMPERATURE (°C)

AV /AV (V)

DD SS

Figure 23. Gain Error vs. Temperature

Figure 20. I_DD/I_SSvs. AV_DD/AV_SS

0.0014

0.0013

0.0012

0.0011

0.0010

0.0009

0.0008

0.0007

0.0006

0.25

0.20

0.15

0.10

0.05

0

T

= 25°C

A

V

= 5V

AV /AV = ±15V

DD SS

REFIN

5V

AV /AV = ±12V

DD SS

–0.05

–0.10

–0.15

–0.20

–0.25

3V

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

–40

–20

0

20

40

60

80

100

V

LOGIC

TEMPERATURE (°C)

Figure 21. Zero-Scale Error vs. Temperature

Figure 24. DI_CCvs. Logic Input Voltage

Rev. F | Page 14 of 28

Data Sheet

AD5764

7000

AV /AV = ±15V

DD SS

T

= 25°C

A

V

= 5V

= 6kΩ

T = 25°C

A

REFIN

RI

6000

5000

4000

3000

2000

1000

0

V

= 5V

SCC

REFIN

AV /AV = ±15V

DD SS

AV /AV = ±12V

DD SS

1

1µs/DIV

CH1 –120mV

–1000

CH1 3.00V

M1.00µs

–10

–5

0

5

10

SOURCE/SINK CURRENT (mA)

Figure 27. Full-Scale Settling Time

Figure 25. Source and Sink Capability of Output Amplifier with

Positive Full Scale Loaded

–4

–6

–8

10000

T

V

= 25°C

A

= 5V

9000

8000

7000

6000

5000

4000

3000

2000

1000

0

REFIN

RI = 6kΩ

SCC

15V SUPPLIES

–10

–12

–14

–16

–18

–20

–22

–24

–26

12V SUPPLIES

AV /AV = ±12V

DD

SS

V

= 5V

REFIN

T

= 25°C

A

0x8000 TO 0x7FFF

500ns/DIV

–1000

–2.0–1.5–1.0–0.5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

TIME (µs)

–12

–7

–2

3

8

SOURCE/SINK CURRENT (mA)

Figure 26. Source and Sink Capability of Output Amplifier with

Negative Full Scale Loaded

Figure 28. Major Code Transition Glitch Energy, AV_DD/AV_SS= 12 V

Rev. F | Page 15 of 28

AD5764

Data Sheet

10

9

8

7

6

5

4

3

2

1

0

AV /AV = ±15V

DD SS

AV /AV = ±15V

DD SS

MIDSCALE LOADED

= 0V

T

= 25°C

A

V

REFIN

V

= 5V

REFIN

4

50µV/DIV

CH4

CH4 50.0µV

M1.00s

26µV

0

20

40

60

(kꢀ)

80

100

120

RI

SCC

Figure 31. Short-Circuit Current vs. RI_SCC

Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth)

T

AV /AV = ±12V

DD

SS

V

= 5V

= 25°C

REFIN

1

2

T

A

RAMP TIME = 100µs

LOAD = 200pF||10kꢀ

3

B

CH1 10.0V

CH2 10.0V

M100µs A CH1

29.60%

7.80mV

W

B

CH3 10.0mV

T

W

Figure 30. V_OUTvs. AV_DD/AV_SSon Power-Up

Rev. F | Page 16 of 28

Data Sheet

AD5764

TERMINOLOGY

Total Unadjusted Error

Relative Accuracy or Integral Nonlinearity (INL)

Total unadjusted error (TUE) is a measure of the output error

considering all the various errors. A plot of total unadjusted

error vs. reference voltage can be seen in Figure 19.

For the DAC, relative accuracy or integral nonlinearity (INL) is

a measure of the maximum deviation, in LꢁBs, from a straight

line passing through the endpoints of the DAC transfer function. A

typical INL vs. code plot can be seen in Figure 7.

Zero-Scale Error Temperature Coefficient (TC)

Zero-scale error TC is a measure of the change in zero-scale

error with a change in temperature. Zero-scale error TC is

expressed in ppm FꢁR/°C.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured

change and the ideal 1 LꢁB change between any two adjacent

codes. A specified differential nonlinearity of 1 LꢁB maximum

ensures monotonicity. This DAC is guaranteed monotonic. A

typical DNL vs. code plot can be seen in Figure 9.

Gain Error Temperature Coefficient (TC)

Gain error TC is a measure of the change in gain error with

changes in temperature. Gain error TC is expressed in

ppm FꢁR/°C.

Monotonicity

A DAC is monotonic if the output either increases or remains

constant for increasing digital input code. The AD5764 is

monotonic over its full operating temperature range.

Digital-to-Analog Glitch Energy

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the data register changes

state. It is normally specified as the area of the glitch in nV-sec,

and is measured when the digital input code is changed by 1 LꢁB at

the major carry transition (ꢀx7FFF to ꢀx8ꢀꢀꢀ); see Figure 28.

Bipolar Zero Error

Bipolar zero error is the deviation of the analog output from the

ideal half-scale output of ꢀ V when the data register is loaded

with ꢀx8ꢀꢀꢀ (offset binary coding) or ꢀxꢀꢀꢀꢀ (twos complement

coding). A plot of bipolar zero error vs. temperature can be seen

in Figure 22.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the DAC

but is measured when the DAC output is not updated. It is speci-

fied in nV-sec and measured with a full-scale code change on

the data bus, that is, from all ꢀs to all 1s, and vice versa.

Bipolar Zero Temperature Coefficient (TC)

Bipolar zero TC is the measure of the change in the bipolar zero

error with a change in temperature. It is expressed in ppm FꢁR/°C.

Power Supply Sensitivity

Power supply sensitivity indicates how the output of the DAC is

affected by changes in the power supply voltage.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale

code is loaded to the data register. Ideally, the output voltage

should be 2 × V_REF− 1 LꢁB. Full-scale error is expressed in

percentage of full-scale range.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in

response to a change in the output of another DAC. It is measured

with a full-scale output change on one DAC while monitoring

another DAC, and is expressed in LꢁBs.

Negative Full-Scale Error/Zero-Scale Error

Negative full-scale error is the error in the DAC output voltage

when ꢀxꢀꢀꢀꢀ (offset binary coding) or ꢀx8ꢀꢀꢀ (twos complement

coding) is loaded to the data register. Ideally, the output voltage

should be −2 × V_REF. A plot of zero-scale error vs. temperature

can be seen in Figure 21.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the

output of one DAC due to a digital code change and subsequent

output change of another DAC. This includes both digital and

analog crosstalk. It is measured by loading one of the DACs with

a full-scale code change (all ꢀs to all 1s and vice versa) with

low and monitoring the output of another DAC. The energy of

the glitch is expressed in nV-sec.

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for the

output to settle to a specified level for a full-scale input change.

LDAC

Slew Rate

The slew rate of a device is a limitation in the rate of change of

the output voltage. The output slewing speed of a voltage-output

DAC is usually limited by the slew rate of the amplifier used at

its output. ꢁlew rate is measured from 1ꢀ% to 9ꢀ% of the output

signal and is given in V/μs.

Channel-to-Channel Isolation

Channel-to-channel isolation is the ratio of the amplitude of the

signal at the output of one DAC to a sine wave on the reference

input of another DAC. It is measured in dB.

Digital Crosstalk

Gain Error

Digital crosstalk is a measure of the impulse injected into the

analog output of one DAC from the digital inputs of another DAC,

but is measured when the DAC output is not updated. It is specified

in nV-sec and measured with a full-scale code change on the data

bus, that is, from all ꢀs to all 1s, and vice versa.

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from the

ideal, expressed as a percentage of the full-scale range. A plot of

gain error vs. temperature can be seen in Figure 23.

Rev. F | Page 17 of 28

AD5764

Data Sheet

THEORY OF OPERATION

The AD5764 is a quad, 16-bit, serial input, bipolar voltage output

DAC and operates from supply voltages of 11.4 V to 16.5 V and

has a buffered output voltage of up to 1ꢀ.5263 V. Data is written to

the AD5764 in a 24-bit word format, via a 3-wire serial interface.

The device also offers an ꢁDO pin that is available for daisy-

chaining or readback.

SERIAꢀ INTERFACE

The AD5764 is controlled over a versatile 3-wire serial interface

that operates at clock rates of up to 3ꢀ MHz and is compatible

with ꢁPI, QꢁPI™, MICROWIRE™, and DꢁP standards.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the

device MꢁB first as a 24-bit word under the control of a serial

clock input, ꢁCLK. The input shift register consists of a read/

write bit, three register select bits, three DAC address bits, and

16 data bits, as shown in Table 9. The timing diagram for this

operation is shown in Figure 2.

The AD5764 incorporates a power-on reset circuit, which ensures

that the data register powers up loaded with ꢀxꢀꢀꢀꢀ. The AD5764

features a digital I/O port that can be programmed via the serial

interface, on-chip reference buffers and per channel digital gain,

and offset registers.

DAC ARCHITECTURE

Upon power-up, the data register is loaded with zero code

(ꢀxꢀꢀꢀꢀ), and the outputs are clamped to ꢀ V via a low imped-

ance path. The outputs can be updated with the zero code value

The DAC architecture of the AD5764 consists of a 16-bit,

current mode, segmented R-2R DAC. The simplified circuit

diagram for the DAC section is shown in Figure 32.

LDAC CLR

at this time by asserting either

or . The corresponding

The four MꢁBs of the 16-bit data word are decoded to drive

15 switches, E1 to E15. Each of these switches connects one of

the 15 matched resistors to either AGNDx or IOUT. The remain-

ing 12 bits of the data-word drive ꢁwitch ꢁꢀ to ꢁwitch ꢁ11 of

the 12-bit R-2R ladder network.

2sCOMP

output voltage depends on the state of the BIN/

pin. If

pin is tied to DGND, the data coding is twos

2sCOMP

the BIN/

complement, and the outputs update to ꢀ V. If the BIN/

pin is tied to DV_CC, the data coding is offset binary, and the

outputs update to negative full scale. To power up the outputs

R

CLR

V

with zero code loaded to the outputs, hold the

during power-up.

pin low

REF

2R

Standalone Operation

R/8

The serial interface works with both a continuous and noncon-

tinuous serial clock. A continuous ꢁCLK source can only be

E15

E14

E1

S0

S11

S10

IOUT

ꢁYNC

used if

In gated clock mode, a burst clock containing the exact number

ꢁYNC

is held low for the correct number of clock cycles.

VOUTx

AGNDx

of clock cycles must be used and

the final clock to latch the data. The first falling edge of

starts the write cycle. Exactly 24 falling clock edges must be

must be taken high after

4 MSBs DECODED INTO

15 EQUAL SEGMENTS

12-BIT, R-2R LADDER

ꢁYNC

Figure 32. DAC Ladder Structure

ꢁYNC

applied to ꢁCLK before

is brought high again. If

is

REFERENCE BUFFERS

brought high before the 24^thfalling ꢁCLK edge, the data written

is invalid. If more than 24 falling ꢁCLK edges are applied before

The AD5764 operates with an external reference. The reference

inputs (REFAB and REFCD) have an input range up to 7 V. This

input voltage is used to provide a buffered positive and negative

reference for the DAC cores. The positive reference is given by

ꢁYNC

is brought high, the input data is also invalid. The input

shift register addressed is updated on the rising edge of

For another serial transfer to take place,

low again. After the end of the serial data transfer, data is

automatically transferred from the input shift register to the

addressed register.

ꢁYNC

must be brought

.

ꢁYNC

+V_REF= 2 × V_REF

The negative reference to the DAC cores is given by

−V_REF= −2 × V_REF

When the data has been transferred into the chosen register of

the addressed DAC, the data register and outputs can be

These positive and negative reference voltages (along with the

gain register values) define the output ranges of the DACs.

LDAC

updated by taking

low.

Rev. F | Page 18 of 28

Data Sheet

AD5764

Daisy-Chain Operation

disable bit; this bit is cleared by default. Readback mode is invoked

W

by setting the R/ bit = 1 in the serial input shift register write.

1

AD5764¹

68HC11

W

With R/ = 1, Bit A2 to Bit Aꢀ, in association with Bit REG2,

MOSI

SCK

SDIN

Bit REG1, and Bit REGꢀ, select the register to be read. The

remaining data bits in the write sequence are don’t cares. During

the next ꢁPI write, the data appearing on the ꢁDO output

contain the data from the previously addressed register. For a

read of a single register, the NOP command can be used in

clocking out the data from the selected register on ꢁDO. The

readback diagram in Figure 4 shows the readback sequence. For

example, to read back the fine gain register of Channel A on the

AD5764, implement the following:

SCLK

SYNC

LDAC

PC7

PC6

MISO

SDO

SDIN

AD5764¹

SCLK

1. Write ꢀxAꢀXXXX to the AD5764 input shift register. This

configures the AD5764 for read mode with the fine gain

register of Channel A selected. Note that all the data bits,

DB15 to DBꢀ, are don’t cares.

SYNC

LDAC

SDO

2. Follow this with a second write, an NOP condition,

ꢀxꢀꢀXXXX. During this write, the data from the fine gain

register is clocked out on the ꢁDO line, that is, data clocked

out contain the data from the fine gain register in Bit DB5

to Bit DBꢀ.

SDIN

AD5764¹

SCLK

SYNC

LDAC

SIMUꢀTANEOUS UPDATING VIA ꢀDAC

SDO

ꢁYNC

LDAC

, and after

Depending on the status of both

and

1

ADDITIONAL PINS OMITTED FOR CLARITY

data has been transferred into the input register of the DACs,

there are two ways in which the data register and DAC outputs

can be updated.

Figure 33. Daisy-Chaining the AD5764

For systems that contain several devices, the ꢁDO pin can be

used to daisy-chain several devices together. This daisy-chain

mode can be useful in system diagnostics and in reducing the

Individual DAC Updating

LDAC

In this mode,

the input shift register. The addressed DAC output is updated

ꢁYNC

is held low while data is being clocked into

ꢁYNC

number of serial interface lines. The first falling edge of

starts the write cycle. The ꢁCLK is continuously applied to the

ꢁYNC

on the rising edge of

Simultaneous Updating of All DACs

LDAC

.

input shift register when

is low. If more than 24 clock

pulses are applied, the data ripples out of the input shift register

and appears on the ꢁDO line. This data is clocked out on the

rising edge of ꢁCLK and is valid on the falling edge. By connect-

ing the ꢁDO of the first device to the ꢁDIN input of the next device

in the chain, a multidevice interface is constructed. Each device in

the system requires 24 clock pulses. Therefore, the total number of

clock cycles must equal 24N, where N is the total number of

AD5764 devices in the chain. When the serial transfer to all

In this mode,

into the input shift register. All DAC outputs are updated by

LDAC ꢁYNC

is held high while data is being clocked

taking

low any time after

has been taken high.

LDAC

The update now occurs on the falling edge of

.

OUTPUT

I/V AMPLIFIER

16-BIT

DAC

V

REFIN

V

OUTx

ꢁYNC

devices is complete,

is taken high. This latches the input

data in each device in the daisy chain and prevents any further

data from being clocked into the input shift register. The serial

clock can be a continuous or a gated clock.

DATA

REGISTER

LDAC

ꢁYNC

A continuous ꢁCLK source can only be used if

is held low

INPUT

REGISTER

for the correct number of clock cycles. In gated clock mode, a burst

clock containing the exact number of clock cycles must be used,

SCLK

SYNC

SDIN

ꢁYNC

and

must be taken high after the final clock to latch the data.

INTERFACE

LOGIC

SDO

Readback Operation

Figure 34. Simplified Serial Interface of Input Loading Circuitry

for One DAC Channel

Before a readback operation is initiated, the ꢁDO pin must be

enabled by writing to the function register and clearing the ꢁDO

Rev. F | Page 19 of 28

AD5764

Data Sheet

The output voltage expression for the AD5764 is given by

TRANSFER FUNCTION

D

65,536

⎡

⎤

Table 7 and Table 8 show the ideal input code to output voltage

relationship for the AD5764 for both offset binary and twos

complement data coding, respectively.

V_OUT= −2×V_REFIN+ 4×V_REFIN

⎢

⎥

⎣

⎦

where:

D is the decimal equivalent of the code loaded to the DAC.

_REFINis the reference voltage applied at the REFAB/REFCD pins.

Table 7. Ideal Output Voltage to Input Code Relationship—

Offset Binary Data Coding

V

Digital Input

Analog Output

MSB

1111

1000

0111

0000

ꢀSB

VOUTx

ASYNCHRONOUS CꢀEAR (CꢀR)

1111

0000

1111

0000

1111

0000

1111

0000

1111

0001

0000

1111

0000

+2 V_REF× (32,767/32,768)

+2 V_REF× (1/32,768)

0 V

CLR

is a negative edge triggered clear that allows the outputs to

be cleared to either ꢀ V (twos complement coding) or negative

CLR

full scale (offset binary coding). It is necessary to maintain

low for a minimum amount of time (see Figure 2) for the operation

−2 V_REF× (1/32,768)

−2 V_REF× (32,767/32,768)

CLR

to complete. When the

remains at the cleared value until a new value is programmed. If

CLR

signal is returned high, the output

Table 8. Ideal Output Voltage to Input Code Relationship—

Twos Complement Data Coding

at power-on,

is at ꢀ V, then all DAC outputs are updated

with the clear value. A clear can also be initiated through software

by writing Command ꢀxꢀ4XXXX to the AD5764.

Digital Input

Analog Output

MSB

0111

0000

1111

1000

ꢀSB

VOUTx

1111

0000

1111

0000

1111

0000

1111

0000

1111

0001

0000

1111

0000

+2 V_REF× (32,767/32,768)

+2 V_REF× (1/32,768)

0 V

−2 V_REF× (1/32,768)

−2 V_REF× (32,767/32,768)

Table 9. Input Shift Register Bit Map

MSB

ꢀSB

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16

DB15:DB0

R/W

0

REG2 REG1 REG0 A2

A1

A0

Data

Table 10. Input Shift Register Bit Functions

Bit

Description

Indicates a read from or a write to the addressed register.

R/W

REG2, REG1, REG0

Used in association with the address bits to determine if a read or write operation is to the data register, offset

register, coarse gain register, fine gain register, or function register.

REG2

REG1

REG0

Function

0

1

0

1

0

1

0

1

Function register

Data register

Coarse gain register

Fine gain register

Offset register

A2, A1, A0

These bits are used to decode the DAC channels.

A2

A1

0

A0

0

Channel Address

DAC A

0

1

DAC B

0

1

0

DAC C

0

1

DAC D

1

0

All DACs

Data

Data bits.

Rev. F | Page 20 of 28

Data Sheet

AD5764

FUNCTION REGISTER

The function register is addressed by setting the three REG bits to ꢀꢀꢀ. The values written to the address bits and the data bits determine

the function addressed. The functions available via the function register are outlined in Table 11 and Table 12.

Table 11. Function Register Options

REG2 REG1 REG0 A2 A1 A0 DB15:DB6 DB5

DB4

DB3

NOP, data = don’t care

D1 value D0 direction

DB2

DB1

DB0

0

1

Don’t care Local ground D1 direction

offset adjust

D0 value

SDO disable

0

1

0

1

Clear, data = don’t care

Load, data = don’t care

Table 12. Explanation of Function Register Options

Option

Description

NOP

No operation instruction used in readback operations.

Local Ground Offset Adjust

Set by the user to enable the local ground offset adjust function. Cleared by the user to disable the local

ground offset adjust function (default). Refer to the Design Features section for further details.

D0/D1 Direction

D0/D1 Value

Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). Refer

to the Design Features section for further details.

I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1

pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is

active as an input. When enabled as inputs, these bits are don’t cares during a write operation.

SDO Disable

Clear

Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).

Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in

binary mode.

Load

Addressing this function updates the data register and consequently the analog outputs.

DATA REGISTER

The data register is addressed by setting the three REG bits to ꢀ1ꢀ. The DAC address bits select with which DAC channel the data transfer

is to take place (see Table 1ꢀ). The data bits are in Position DB15 to Position DBꢀ, as shown in Table 13.

Table 13. Programming the Data Register Bit Map

REG2

REG1

REG0

A2

A1

A0

DB15:DB0

0

1

0

DAC address

16-bit DAC data

COARSE GAIN REGISTER

The coarse gain register is addressed by setting the three REG bits to ꢀ11. The DAC address bits select with which DAC channel the data

transfer is to take place (see Table 1ꢀ). The coarse gain register is a 2-bit register and allows the user to select the output range of each

DAC, as shown in Table 14 and Table 15.

Table 14. Programming the Coarse Gain Register Bit Map

REG2

REG1

REG0

A2

A1

A0

DB15: DB2

DB1

DB0

0

1

DAC address

Don’t care

CG1

CG0

Table 15. Output Range Selection

Output Range

CG1

CG0

10 V (Default)

10.2564 V

10.5263 V

0

1

0

1

0

Rev. F | Page 21 of 28

AD5764

Data Sheet

FINE GAIN REGISTER

OFFSET REGISTER

The fine gain register is addressed by setting the three REG bits

to 1ꢀꢀ. The DAC address bits select with which DAC channel

the data transfer is to take place (see Table 1ꢀ). The fine gain

register is a 6-bit register and allows the user to adjust the gain

of each DAC channel by −32 LꢁBs to +31 LꢁBs in 1 LꢁB

increments, as shown in Table 16 and Table 17. The adjustment

is made to both the positive full-scale points and the negative

full-scale points simultaneously, each point being adjusted by ½

of one step. The fine gain register coding is twos complement.

The offset register is addressed by setting the three REG bits to

1ꢀ1. The DAC address bits select with which DAC channel the

data transfer is to take place (see Table 1ꢀ). The AD5764 offset

register is an 8-bit register and allows the user to adjust the offset

of each channel by −16 LꢁBs to +15.875 LꢁBs in increments of

⅛ LꢁB, as shown in Table 18 and Table 19. The offset register

coding is twos complement.

Table 16. Programming the Fine Gain Register Bit Map

REG2

REG1

REG0

A2

A1

A0

DB15:DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

DAC address

Don’t care

FG5

FG4

FG3

FG2

FG1

FG0

Table 17. Fine Gain Register Options

Gain Adjustment

+31 LSBs

+30 LSBs

…

FG5

0

…

0

FG4

1

…

0

FG3

1

…

0

FG2

1

…

0

FG1

FG0

1

…

1

0

…

0

+2 LSBs

+1 LSB

0

1

No Adjustment (Default)

−1 LSB

0

1

0

1

0

1

0

1

0

1

0

1

−2 LSBs

1

0

…

−31 LSBs

−32 LSBs

…

1

…

0

…

0

…

0

…

0

…

1

0

Table 18. Programming the Offset Register Bit Map

REG2

REG1

REG0

A2

A1

A0

DB15:DB8

DB7

DB6

DB5

OF5

DB4

OF4

DB3

DB2

OF2

DB1

DB0

1

0

1

DAC address

Don’t care

OF7

OF6

OF3

OF1

OF0

Table 19. AD5764 Offset Register Options

Offset Adjustment

+15.875 LSBs

+15.75 LSBs

…

OF7

0

…

0

OF6

1

…

0

OF5

1

…

0

OF4

OF3

OF2

1

…

0

OF1

OF0

1

…

0

1

…

0

1

…

1

0

…

0

+0.25 LSBs

+0.125 LSBs

No Adjustment (Default)

−0.125 LSBs

−0.25 LSBs

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

…

1

…

0

…

0

…

0

…

0

…

0

…

0

…

1

0

−15.875 LSBs

−16 LSBs

Rev. F | Page 22 of 28

Data Sheet

AD5764

Convert this to a negative twos complement number by inverting

all bits and adding 1 to obtain 1111ꢀꢀꢀꢀ, the value that should

be programmed to the offset register.

OFFSET AND GAIN ADJUSTMENT WORKED

EXAMPꢀE

Using the information provided in the Fine Gain Register and

Offset Register sections, the following worked example demon-

strates how the AD5764 functions can be used to eliminate both

offset and gain errors. Because the AD5764 is factory calibrated,

offset and gain errors should be negligible. However, errors can

be introduced by the system that the AD5764 is operating within;

for example, a voltage reference value that is not equal to 5 V

introduces a gain error. An output range of 1ꢀ V and twos

complement data coding is assumed.

Note that this twos complement conversion is not necessary in the

case of a positive offset adjustment. The value to be programmed to

the offset register is simply the binary representation of the

adjustment value.

Removing Gain Error

The AD5764 can eliminate a gain error at negative full-scale

output in the range of −9.77 mV to +9.46 mV with a step size of

½ of a 16-bit LꢁB.

Removing Offset Error

Calculate the step size of the gain adjustment.

2ꢀ

The AD5764 can eliminate an offset error in the range of −4.88 mV

to +4.84 mV with a step size of ⅛ of a 16-bit LꢁB.

GainAdjust StepSize =

=152.59 ꢂV

2¹⁶× 2

Calculate the step size of the offset adjustment.

Measure the gain error by programming ꢀx8ꢀꢀꢀ to the data

register and measuring the resulting output voltage. The gain

error is the difference between this value and −1ꢀ V. For this

example, the gain error is −1.2 mV.

2ꢀ

Offset Adjust Step Size =

= 38.14 ꢂV

2

¹⁶×8

Measure the offset error by programming ꢀxꢀꢀꢀꢀ to the data

register and measuring the resulting output voltage. For this

example, the measured value is 614 μV.

Calculate how many gain adjustment steps this value represents.

Measured Gain Value

Number of Steps =

=

Calculate the number of offset adjustment steps that this value

represents.

Gain Step Size

1.2 mV

= 8 ꢁteps

152.59 ꢂV

Measured Offset Value

Numberof Steps =

=

Offset Step Size

The gain error measured is negative (in terms of magnitude);

therefore, a positive adjustment of eight steps is required. The

gain register is 6 bits wide and the coding is twos complement,

the required gain register value can be determined as follows:

Convert the adjustment value to binary: ꢀꢀ1ꢀꢀꢀ.

The value to be programmed to the gain register is simply this

binary number.

614 ꢂV

= 16 ꢁteps

38.14 ꢂV

The offset error measured is positive, therefore, a negative

adjustment of 16 steps is required. The offset register is eight

bits wide and the coding is twos complement. The required

offset register value can be calculated as follows:

Convert the adjustment value to binary: ꢀꢀꢀ1ꢀꢀꢀꢀ.

Rev. F | Page 23 of 28

AD5764

Data Sheet

DESIGN FEATURES

ANAꢀOG OUTPUT CONTROꢀ

PROGRAMMABꢀE SHORT-CIRCUIT PROTECTION

The short-circuit current of the output amplifiers can be pro-

grammed by inserting an external resistor between the IꢁCC

pin and PGND. The programmable range for the current is 5ꢀꢀ μA

to 1ꢀ mA, corresponding to a resistor range of 12ꢀ kΩ to 6 kΩ.

The resistor value is calculated as follows:

In many industrial process control applications, it is vital that

the output voltage be controlled during power-up and during

brownout conditions. When the supply voltages are changing,

the VOUTx pins are clamped to ꢀ V via a low impedance path.

To prevent the output amp being shorted to ꢀ V during this time,

Transmission Gate G1 is also opened (see Figure 35). These condi-

tions are maintained until the power supplies stabilize and a

valid word is written to the data register. At this time, G2 opens and

G1 closes. Both transmission gates are also externally controllable

6ꢀ

I_ꢁC

R =

If the IꢁCC pin is left unconnected, the short-circuit current

limit defaults to 5 mA. Note that limiting the short-circuit

current to a small value can affect the slew rate of the output

when driving into a capacitive load; therefore, the value of the

programmed short circuit should take into account the size of

the capacitive load being driven.

RꢁTIN

input is

via the reset logic (

) control input. For instance, if

RꢁTIN

is driven from a battery supervisor chip, the

driven low to open G1 and close G2 upon power-down or during

a brownout. Conversely, the on-chip voltage detector output

RꢁTOUT

(

) is also available to the user to control other parts of

DIGITAꢀ I/O PORT

the system. The basic transmission gate functionality is shown

in Figure 35.

The AD5764 contains a 2-bit digital I/O port (D1 and Dꢀ).

These bits can be configured as inputs or outputs independently,

and can be driven or have their values read back via the serial

interface. The I/O port signals are referenced to DV_CCand DGND.

When configured as outputs, they can be used as control signals

to multiplexers or can be used to control calibration circuitry

elsewhere in the system. When configured as inputs, the logic

signals from limit switches can, for example, be applied to Dꢀ

and D1 and can be read back via the digital interface.

RSTOUT

RSTIN

VOLTAGE

MONITOR

AND

CONTROL

G1

VOUTA

AGNDA

G2

ꢀOCAꢀ GROUND OFFSET ADJUST

The AD5764 incorporates a local ground offset adjust feature

that, when enabled in the function register, adjusts the DAC

outputs for voltage differences between the individual DAC ground

pins, AGNDx, and the REFGND pin, ensuring that the DAC

output voltages are always with respect to the local DAC ground

pin. For instance, if Pin AGNDA is at +5 mV with respect to the

REFGND pin and VOUTA is measured with respect to AGNDA,

a −5 mV error results, enabling the local ground offset adjust

feature to adjust VOUTA by +5 mV, eliminating the error.

Figure 35. Analog Output Control Circuitry

DIGITAꢀ OFFSET AND GAIN CONTROꢀ

The AD5764 incorporates a digital offset adjust function with a

16 LꢁB adjust range and ꢀ.125 LꢁB resolution. The coarse gain

register allows the user to adjust the AD5764 full-scale output

range. The full-scale output can be programmed to achieve full-

scale ranges of 1ꢀ V, 1ꢀ.2564 V, and 1ꢀ.5263 V. A fine gain

trim is also provided.

Rev. F | Page 24 of 28

Data Sheet

AD5764

APPLICATIONS INFORMATION

reference and associated buffers. This leads to an overall savings

in both cost and board space.

TYPICAꢀ OPERATING CIRCUIT

Figure 36 shows the typical operating circuit for the AD5764.

The only external components needed for this precision 16-bit

DAC are a reference voltage source, decoupling capacitors on

the supply pins and reference inputs, and an optional short-

circuit current setting resistor. Because the device incorporates

reference buffers, it eliminates the need for an external bipolar

In Figure 36, AV_DDis connected to +15 V and AV_ꢁꢁis connected

to −15 V. However, AV_DDcan operate with supplies from +11.4 V

to +16.5 V and AV_ꢁꢁcan operate with supplies from −11.4 V to

−16.5 V.

+15V

ADR02

VIN VOUT

GND

2

6

4

+15V –15V

10µF

100nF

BIN/2sCOMP

32 31 30 29 28 27 26 25

+5V

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

SYNC

SCLK

SDIN

SDO

SYNC

AGNDA

VOUTA

VOUTB

AGNDB

AGNDC

VOUTC

VOUTD

AGNDD

SCLK

SDIN

SDO

CLR

LDAC

D0

VOUTA

VOUTB

AD5764

LDAC

D0

VOUTC

VOUTD

D1

9

10 11 12 13 14 15 16

RSTOUT

RSTIN

10µF

100nF

NC = NO CONNECT

10µF

+5V

+15V –15V

Figure 36. Typical Operating Circuit

Rev. F | Page 25 of 28

AD5764

Data Sheet

Precision Voltage Reference Selection

voltage to a voltage other than the nominal. The trim adjust-

ment can also be used at temperature to trim out any error.

To achieve the optimum performance from the AD5764 over its

full operating temperature range, a precision voltage reference

must be used. Consideration should be given to the selection of

a precision voltage reference. The AD5764 has two reference

inputs, REFAB and REFCD. The voltages applied to the refer-

ence inputs are used to provide a buffered positive and negative

reference for the DAC cores. Therefore, any error in the voltage

reference is reflected in the outputs of the device.

Long-term drift is a measure of how much the reference output

voltage drifts over time. A reference with a tight long-term drift

specification ensures that the overall solution remains relatively

stable over its entire lifetime.

The temperature coefficient of a reference output voltage affects

INL, DNL, and TUE. Choose a reference with a tight temperature

coefficient specification to reduce the dependence of the DAC

output voltage on ambient conditions.

There are four possible sources of error to consider when

choosing a voltage reference for high accuracy applications:

initial accuracy, temperature coefficient of the output voltage,

long-term drift, and output voltage noise.

In high accuracy applications, which have a relatively low noise

budget, reference output voltage noise needs to be considered.

Choosing a reference with as low an output noise voltage as

practical for the system resolution required is important. Precision

voltage references such as the ADR435 (XFET® design) produce

low output noise in the ꢀ.1 Hz to 1ꢀ Hz region. However, as the

circuit bandwidth increases, filtering the output of the reference

may be required to minimize the output noise.

Initial accuracy error on the output voltage of an external refer-

ence can lead to a full-scale error in the DAC. Therefore, to

minimize these errors, a reference with low initial accuracy

error specification is preferred. Choosing a reference with an

output trim adjustment, such as the ADR425, allows a system

designer to trim system errors out by setting the reference

Table 20. Some Precision References Recommended for Use with the AD5764

Part No. Initial Accuracy (mV Max) ꢀong-Term Drift (ppm Typ) Temp Drift (ppm/°C Max) 0.1 Hz to 10 Hz Noise (μV p-p Typ)

ADR435

ADR425

ADR02

2

5

40

50

3

9

8

3.4

10

8

ADR395

Rev. F | Page 26 of 28

Data Sheet

AD5764

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure the

rated performance. The PCB on which the AD5764 is mounted

must be designed so that the analog and digital sections are sepa-

rated and confined to certain areas of the board. If the AD5764 is

in a system where multiple devices require an AGND-to-DGND

connection, the connection is to be made at one point only. The

star ground point is established as close as possible to the device.

The AD5764 must have ample supply bypassing of 1ꢀ μF in parallel

with ꢀ.1 μF on each supply, located as close to the package as

possible, ideally right up against the device. The 1ꢀ μF capacitors

are the tantalum bead type. The ꢀ.1 μF capacitor must have low

effective series resistance (EꢁR) and low effective series inductance

(EꢁI), such as the common ceramic types, which provide a low

impedance path to ground at high frequencies to handle transient

currents due to internal logic switching.

interfaces because the number of interface lines is kept to a

minimum. Figure 37 shows a 4-channel isolated interface to the

AD5764 using an ADuM14ꢀꢀ. For more information, go to

www.analog.com.

MICROCONTROLLER

ADuM1400*

V_OA

V_IA

SERIAL CLOCK

ENCODE

DECODE

TO SCLK

TO SDIN

TO SYNC

TO LDAC

OUT

V_OB

V_OC

V_OD

V_IB

V_IC

V_ID

SERIAL DATA

OUT

SYNC OUT

CONTROL OUT

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 37. Isolated Interface

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5764 is via a serial bus

that uses a standard protocol that is compatible with micro-

controllers and DꢁP processors. The communications channel

is a 3-wire (minimum) interface consisting of a clock signal, a

data signal, and a synchronization signal. The AD5764 requires

a 24-bit data-word with data valid on the falling edge of ꢁCLK.

The power supply lines of the AD5764 must be as large a trace

as possible to provide low impedance paths and reduce the effects

of glitches on the power supply line. Fast switching signals, such as

clocks, must be shielded with digital ground to avoid radiating

noise to other parts of the board, and must never be run near

the reference inputs. A ground line routed between the ꢁDIN

and ꢁCLK lines helps reduce crosstalk between them (not required

on a multilayer board, which has a separate ground plane; however,

it is helpful to separate the lines). It is essential to minimize noise

on the reference inputs because it couples through to the DAC

output. Avoid crossover of digital and analog signals. Traces on

opposite sides of the board must run at right angles to each other.

This reduces the effects of feedthrough on the board. A microstrip

technique is recommended, but not always possible with a double-

sided board. In this technique, the component side of the board

is dedicated to the ground plane, and signal traces are placed on

the solder side.

For all the interfaces, the DAC output update can be performed

automatically when all the data is clocked in, or it can be done

LDAC

under the control of

. The contents of the data register

can be read using the readback function.

EVAꢀUATION BOARD

The AD5764 comes with a full evaluation board to aid designers

in evaluating the high performance of the part with minimum

effort. All that is required with the evaluation board is a power

supply and a PC. The AD5764 evaluation kit includes a populated,

tested AD5764 PCB. The evaluation board interfaces to the UꢁB

port of the PC. ꢁoftware is available with the evaluation board,

which allows the user to easily program the AD5764. The software

runs on any PC that has Microsoft® Windows® 2ꢀꢀꢀ/NT/XP

installed.

GAꢀVANICAꢀꢀY ISOꢀATED INTERFACE

In many process control applications, it is necessary to provide

an isolation barrier between the controller and the unit being

controlled to protect and isolate the controlling circuitry from

any hazardous common-mode voltages that may occur. Isocoup-

lers provide voltage isolation in excess of 2.5 kV. The serial

loading structure of the AD5764 makes it ideal for isolated

The EVAL-AD5764EB data sheet is available, which gives full

details on the operation of the evaluation board.

Rev. F | Page 27 of 28

AD5764

Data Sheet

OUTLINE DIMENSIONS

1.20

MAX

0.75

0.60

0.45

9.00 BSC SQ

25

32

1

24

PIN 1

7.00

BSC SQ

TOP VIEW

(PINS DOWN)

0° MIN

1.05

1.00

0.95

0.20

0.09

7°

8

17

3.5°

0°

0.15

0.05

9

16

SEATING

PLANE

0.08 MAX

COPLANARITY

VIEW A

0.80

0.45

0.37

0.30

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-ABA

Figure 38. 32-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

AD5764ASUZ

AD5764ASUZ-REEL7

AD5764BSUZ

AD5764BSUZ-REEL7

AD5764CSUZ

INꢀ

4 LSB max

Temperature Range

−40°C to +85°C

Package Description

32-Lead TQFP

Evaluation Board

Package Option

SU-32-2

4 LSB max

2 LSB max

1 LSB max

AD5764CSUZ-REEL7

EVAL-AD5764EBZ

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D05303-0-9/11(F)

Rev. F | Page 28 of 28

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