AD708JNZ各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号AD708JNZ的概述

AD708JNZ芯片概述 AD708JNZ是一款高精度、低功耗的运算放大器，设计用于各类精密信号处理应用。其高输入阻抗和低输入失调电压特性使得该芯片在测量和数据采集系统中尤为重要。AD708系列芯片广泛应用于医疗仪器、工业控制、数据采集系统及通信设备等领域，满足多种复杂电路的需求。详细参数 AD708JNZ的关键技术参数如下： - 工作电源电压(V)：单电源电压范围为±2V到±15V，适应多种工作环境。 - 输入失调电压(mV)：典型值为0.5mV，最大值为2mV，这意味着其适合于对高精度要求的电路。 - 输入阻抗(MΩ)：输入阻抗高达10 MΩ，这显示出其在信号传输过程中的优越性能。 - 增益带宽积(MHz)：可以达到1MHz，适合于高频信号的处理需求。 - 输出电流(mA)：最大输出电流为20mA，在驱动负载方面具备良好性能。 - 共模抑制比(CMRR)：典型值为100dB，展示...

产品型号AD708JNZ的Datasheet PDF文件预览

Ultralow Offset Voltage

Dual Op Amp

AD708

FEATURES

PIN CONFIGURATION

Very high dc precision

30 μV maximum offset voltage

0.3 μV/°C maximum offset voltage drift

0.35 μV p-p maximum voltage noise (0.1 Hz to 10 Hz)

5 million V/V minimum open-loop gain

130 dB minimum CMRR

AD708

OUTPUT A

–IN A

OUTPUT B

–IN B

^–A

+IN A

B ^–

–V

+IN B

TOP VIEW

(Not to Scale)

120 dB minimum PSRR

Matching characteristics

Figure 1. PDIP (N) and CERDIP (Q) Packages

30 μV maximum offset voltage match

0.3 μV/°C maximum offset voltage drift match

130 dB minimum CMRR match

Available in 8-lead narrow body, PDIP, and

hermetic CERDIP and CERDIP/883B packages

GENERAL DESCRIPTION

The AD708 is a high precision, dual monolithic operational

amplifier. Each amplifier individually offers excellent dc

precision with maximum offset voltage and offset voltage drift

of any dual bipolar op amp.

The AD708S is rated over the military temperature range of

−55°C to +125°C and is available in a CERDIP military version

processed to MIL-STD-883B.

PRODUCT HIGHLIGHTS

The matching specifications are among the best available in any

dual op amp. In addition, the AD708 provides 5 V/μV mini-

mum open-loop gain and guaranteed maximum input voltage

noise of 350 nV p-p (0.1 Hz to 10 Hz). All dc specifications

show excellent stability over temperature, with offset voltage

drift typically 0.1 μV/°C and input bias current drift of

25 pA/°C maximum.

1. The combination of outstanding matching and individual

specifications make the AD708 ideal for constructing high

gain, precision instrumentation amplifiers.

2. The low offset voltage drift and low noise of the AD708

allow the designer to amplify very small signals without

sacrificing overall system performance.

The AD708 is available in four performance grades. The

AD708J is rated over the commercial temperature range of

0°C to 70°C and is available in a narrow body, PDIP. The

AD708A and AD708B are rated over the industrial temperature

range of −40°C to +85°C and are available in a CERDIP.

3. The AD708 10 V/ꢀV typical open-loop gain and 140 dB

common-mode rejection make it ideal for precision

applications.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD708

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 10

Crosstalk Performance .............................................................. 10

Operation with a Gain of −100................................................. 11

High Precision Programmable Gain Amplifier ..................... 11

Bridge Signal Conditioner......................................................... 12

Precision Absolute Value Circuit ............................................. 12

Selection of Passive Components............................................. 12

Outline Dimensions....................................................................... 13

Ordering Guide .......................................................................... 13

Pin Configuration............................................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Typical Performance Characteristics ............................................. 6

Matching Characteristics............................................................. 9

REVISION HISTORY

1/06—Rev. B to Rev. C

Updated Format..................................................................Universal

Removed TO-99 Package ..................................................Universal

Deleted AD707 References................................................Universal

Deleted LT1002 Reference............................................................... 1

Deleted Figure 1................................................................................ 1

Deleted Metalization Photograph .................................................. 5

Moved Figure 25, Figure 26, and Figure 27

to Theory of Operation section .................................................... 10

Updated Outline Dimensions....................................................... 13

Changes to Ordering Guide .......................................................... 13

2/91—Rev. A to Rev. B

Rev. C | Page 2 of 16

AD708

SPECIFICATIONS

@ 25°C and 15 V dc, unless otherwise noted.

Table 1.

AD708J/AD708A

AD708B

AD708S

Parameter

INPUT OFFSET VOLTAGE²

Conditions

T_MINto T_MAX

Min¹Typ Max¹Min¹Typ Max¹Min¹Typ Max¹Unit

0.3

1.0

2.0

0.5

2.0

μV

μV/°C

μV/month

pA/°C

100

150

1.0

0.4

0.3

0.1

0.3

0.5

1.0

0.1

0.2

0.1

0.3

0.5

1.0

0.1

0.2

Drift

Long Term Stability

INPUT BIAS CURRENT

2.5

4.0

1.0

2.0

1.5

T_MINto T_MAX

Average Drift

OFFSET CURRENT

V_CM= 0 V

T_MINto T_MAX

2.0

4.0

1.0

1.5

Average Drift

MATCHING CHARACTERISTICS³

Offset Voltage

μV

T_MINto T_MAX

150

1.0

4.0

5.0

μV

μV/°C

Offset Voltage Drift

Input Bias Current

0.4

1.0

2.0

0.3

1.0

2.0

T_MINto T_MAX

Common-Mode Rejection

Power Supply Rejection

140

120

110

135

130

120

140

130

120

140

Channel Separation

INPUT VOLTAGE NOISE

0.1 Hz to 10 Hz

f = 10 Hz

f = 100 Hz

f = 1 kHz

0.23 0.6

10.3 18

10.0 13.0

0.23 0.6

10.3 12

10.0 11.0

0.23

10.3 12

10.0 11

9.6

0.32 0.8

0.14 0.23

0.12 0.17

140

μV p-p

nV/√Hz

pA p-p

pA/√Hz

0.35

9.6

11.0

9.6

11.0

INPUT CURRENT NOISE

0.1 Hz to 10 Hz

f = 10 Hz

f = 100 Hz

f = 1 kHz

0.32 0.9

0.14 0.27

0.12 0.18

140

0.32 0.8

0.14 0.23

0.12 0.17

140

COMMON-MODE REJECTION RATIO V_CM= 13 V

T_MINto T_MAX

120

130

140

OPEN-LOOP GAIN

V_O= 10 V

R_LOAD≥ 2 kΩ

T_MINto T_MAX

V/μV

POWER SUPPLY REJECTION RATIO

V_S= 3 V to 18 V

T_MINto T_MAX

130

110

120

FREQUENCY RESPONSE

Closed-Loop Bandwidth

Slew Rate

0.5

0.15

0.9

0.3

0.5

0.15

0.9

0.3

0.5

0.15

0.9

0.3

MHz

V/μs

INPUT RESISTANCE

Differential

200

400

200

400

MΩ

GΩ

Common Mode

Rev. C | Page 3 of 16

AD708

AD708J/AD708A

AD708B

AD708S

Parameter

Conditions

R_LOAD≥ 10 kΩ

R_LOAD≥ 2 kΩ

R_LOAD≥ 1 kΩ

T_MINto T_MAX

Min¹Typ Max¹Min¹Typ Max¹Min¹Typ Max¹Unit

OUTPUT VOLTAGE

14.0

13.0

12.5

13.0

12.5

13.5

12.5

12.0

13.5

12.5

12.0

13.5

12.5

12.0

13.0

12.5

13.0

OPEN-LOOP OUTPUT RESISTANCE

POWER SUPPLY

Quiescent Current

Power Consumption

4.5

135

5.5

165

4.5

135

5.5

165

4.5

135

5.5

165

V_S= 15 V

V_S= 3 V

Operating Range

¹All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to

calculate outgoing quality levels.

²Input offset voltage specifications are guaranteed after five minutes of operation at T_A= 25°C.

³Matching is defined as the difference between parameters of the two amplifiers.

Rev. C | Page 4 of 16

AD708

ABSOLUTE MAXIMUM RATINGS

Table 2.

Stresses above those listed under Absolute Maximum Ratings

Parameter

Rating

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Supply Voltage

Internal Power Dissipation¹

Input Voltage²

22 V

V_S

Output Short-Circuit Duration

Differential Input Voltage

Storage Temperature Range (Q)

Storage Temperature Range (N)

Lead Temperature (Soldering 60 sec)

Indefinite

+V_Sand −V_S

−65°C to +150°C

−65°C to +125°C

300°C

¹Thermal Characteristics

8-lead PDIP: θ_JC= 33°C/W, θ_JA= 100°C/W

8-lead CERDIP: θ_JC= 30°C/W, θ_JA= 110°C/W

²For supply voltages less than 22 V, the absolute maximum input voltage is

equal to the supply voltage.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. C | Page 5 of 16

AD708

TYPICAL PERFORMANCE CHARACTERISTICS

V_S= 15 V and T_A= 25°C, unless otherwise noted.

–0.5

–1.0

–1.5

1.5

1.0

–V

0.5

–V

SUPPLY VOLTAGE (±V)

Figure 2. Input Common-Mode Range vs. Supply Voltage

Figure 5. Supply Current vs. Supply Voltage

100

256 UNITS TESTED

–55°C TO +125°C

–0.5

OUT

–1.0

–1.5

= 10kΩ

= 2kΩ

1.5

1.0

0.5

–V

OUT

–V

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

SUPPLY VOLTAGE (±V)

OFFSET VOLTAGE DRIFT (µV/°C)

Figure 3. Output Voltage Swing vs. Supply Voltage

Figure 6. Typical Distribution of Offset Voltage Drift

100

= 1mA

= +1000

= +1

±15V SUPPLIES

0.1

0.01

0.001

0.0001

100

10k

0.1

100

FREQUENCY (Hz)

10k

100k

LOAD RESISTANCE (Ω)

Figure 7. Output Impedance vs. Frequency

Figure 4. Output Voltage Swing vs. Load Resistance

Rev. C | Page 6 of 16

AD708

= ±10V

OUT

= 10kΩ

= 2kΩ

100

–60 –40 –20

100 120 140

DIFFERENTIAL VOLTAGE (±V)

TEMPERATURE (°C)

Figure 11. Open-Loop Gain vs. Temperature

Figure 8. Input Bias Current vs. Differential Input Voltage

= 2kΩ

LOAD

1/F CORNER

0.7Hz

0.1

100

SUPPLY VOLTAGE (V)

FREQUENCY (Hz)

Figure 9. Input Noise Spectral Density

Figure 12. Open-Loop Gain vs. Supply Voltage

140

120

100

= 2kꢀ

= 1000pF

PHASE

MARGIN = 43°

120

150

180

GAIN

–20

0.01 0.1

100

10k 100k 1M 10M

TIME (1s/DIV)

FREQUENCY (Hz)

Figure 10. 0.1 Hz to 10 Hz Voltage Noise

Figure 13. Open-Loop Gain and Phase vs. Frequency

Rev. C | Page 7 of 16

AD708

160

140

120

100

2mV/DIV

CH1

0.1

TIME (2µs/DIV)

100

10k

100k

FREQUENCY (Hz)

Figure 14. Common-Mode Rejection vs. Frequency

Figure 17. Small Signal Transient Response; A_V= +1, R_L= 2 kΩ, C_L= 50 pF

= 2kꢀ

25°C

= ±15V

= 2.8kHz

MAX

2mV/DIV

CH1

TIME (2µs/DIV)

10k

100k

FREQUENCY (Hz)

Figure 18. Small Signal Transient Response; A_V= +1, R_L= 2 kΩ, C_L= 1000 pF

Figure 15. Large Signal Frequency Response

160

140

120

100

0.001

0.01

0.1

100

10k

100k

FREQUENCY (Hz)

Figure 16. Power Supply Rejection vs. Frequency

Rev. C | Page 8 of 16

AD708

MATCHING CHARACTERISTICS

25°C

–50 –40 –30 –20 –10

–1.0 –0.8 –0.6 –0.4 –0.2

0.2

0.4

0.6

0.8

1.0

OFFSET VOLTAGE MATCH (µV)

OFFSET CURRENT MATCH (nA)

Figure 19. Typical Distribution of Offset Voltage Match

Figure 22. Typical Distribution of Input Offset Current Match

160

140

120

100

–55°C TO +125°C

–0.5 –0.4 –0.3 –0.2 –0.1

0.1

0.2

0.3

0.4

0.5

–60 –40 –20

100 120 140

OFFSET DRIFT MATCH (µV/°C)

TEMPERATURE (°C)

Figure 20. Typical Distribution of Offset Voltage Drift Match

Figure 23. PSRR Match vs. Temperature

160

140

120

100

–1.0 –0.8 –0.6 –0.4 –0.2

0.2

0.4

0.6

0.8

1.0

–60 –40 –20

100 120 140

INPUT BIAS CURRENT MATCH (nA)

TEMPERATURE (°C)

Figure 21. Typical Distribution of Input Bias Current Match

Figure 24. CMRR Match vs. Temperature

Rev. C | Page 9 of 16

AD708

THEORY OF OPERATION

CROSSTALK PERFORMANCE

The AD708 exhibits very low crosstalk as shown in Figure 25,

Figure 26, and Figure 27. Figure 25 shows the offset voltage

induced on Side B of the AD708 when Side A output is moving

slowly (0.2 Hz) from −10 V to +10 V under no load. This is the

least stressful situation to the part because the overall power in

the chip does not change. Only the location of the power in the

output device changes. Figure 26 shows the input offset voltage

change to Side B when Side A is driving a 2 kΩ load. Here the

power changes in the chip with the maximum power change

occurring at 7.5 V. Figure 27 shows crosstalk under the most

severe conditions. Side A is connected as a follower with

0 V input, and is forced to sink and source 5 mA of output

current.

OUTA

= ±10V

2kꢀ

10kꢀ

OUTB

10ꢀ

Power = (30 V)(5 mA) = 150 mW

Even this large change in power causes only an 8 μV (linear)

change in the input offset voltage of Side B.

OUTA

= ±10V

= 2V/DIV

10kꢀ

OUTA

Figure 26. Crosstalk with 2 kΩ Load

OUTB

10ꢀ

= ±5mA

2kꢀ

= ±10V

10kꢀ

OUTB

10ꢀ

= 2V/DIV

OUTA

Figure 25. Crosstalk with No Load

IN = 1mA/DIV

Figure 27. Crosstalk Under Forced Source and Sink Conditions

Rev. C | Page 10 of 16

AD708

1/2

AD708

OPERATION WITH A GAIN OF −100

INA

To show the outstanding dc precision of the AD708 in a real

application, Table 3 shows an error budget calculation for a gain

of −100. This configuration is shown in Figure 28.

OUT

1–4

10kꢀ

9.9kꢀ

Table 3.

10kꢀ

Maximum Error Contribution

A_V= 100 (S Grade)

(Full Scale: V_OUT= 10 V, V_IN= 100 mV)

AD7502

AD707

100ꢀ

1kꢀ

10kꢀ

–V

Error Sources

9.9kꢀ

V_OS

30 μV/100 mV

= 300 ppm

= 10 ppm

= 20 ppm

= 4 ppm

I_OS

(100 kΩ)(1 nA)/10 V

10 V/(5 × 106)/100 mV

0.35 mV/100 mV

OUT

5–8

10kꢀ

Gain (2 kΩ Load)

Noise

INB

1/2

AD708

V_OSDrift

(0.3 mV/°C)/100 mV

= 3 ppm/°C

Total Unadjusted

Error

Figure 29. Precision PGA

@ 25°C

= 334 ppm > 11 bits

= 634 ppm > 10 bits

The gains of the circuit are controlled by the select lines, A0 and

A1, of the AD7502 multiplexer, and are 1, 10, 100, and 1000 in

this design.

−55°C to +125°C

With Offset

Calibrated Out @ 25°C

−55°C to +125°C

= 34 ppm > 14 bits

= 334 ppm > 11 bits

The input stage attains very high dc precision due to the 30 μV

maximum offset voltage match of the AD708S and the 1 nA

maximum input bias current match. The accuracy is main-

tained over temperature because of the ultralow drift

performance of the AD708.

100kꢀ

0.1µF

1kꢀ

To achieve 0.1% gain accuracy, along with high common-mode

rejection, the circuit should be trimmed.

–

1/2

AD708

OUT

To maximize common-mode rejection

1kꢀ

1. Set the select lines for gain = 1 and ground V_INB

–V

2. Apply a precision dc voltage to V_INAand trim R_Auntil

V_O= −V_INAto the required precision.

Figure 28. Gain of −100 Configuration

This error budget assumes no error in the resistor ratio and no

error from power supply variation (the 120 dB minimum PSRR

of the AD708S makes this a good assumption). The external

resistors can cause gain error from mismatch and drift over

temperature.

3. Connect V_INBto V_INAand apply an input voltage equal to

the full-scale common mode expected.

4. Trim R_Buntil V_O= 0 V.

To minimize gain errors

HIGH PRECISION PROGRAMMABLE GAIN

AMPLIFIER

1. Select gain = 10 with the control lines and apply a

differential input voltage.

The three op amp programmable gain amplifier shown in

Figure 29 takes advantage of the outstanding matching

characteristics of the AD708 to achieve high dc precision.

2. Adjust the 100 Ω potentiometer to V_O= 10 V_IN

(adjust V_INmagnitude as necessary).

3. Repeat Step 1 and Step 2 for gain = 100 and gain = 1000,

adjusting the 1 kΩ and 10 kΩ potentiometers, respectively.

The design shown in Figure 29 should allow for 0.1% gain

accuracy and 0.1 μV/V common-mode rejection when 1%

resistors and 5% potentiometers are used.

Rev. C | Page 11 of 16

AD708

AD708 enables this circuit to accurately resolve the input signal.

In addition, the tight offset voltage drift match maintains the

resolution of the circuit over the full military temperature

range. The high dc open-loop gain and exceptional gain

linearity allows the circuit to perform well at both large and

small signal levels.

BRIDGE SIGNAL CONDITIONER

The AD708 can be used in the circuit shown in Figure 30 to

produce an accurate and inexpensive dynamic bridge condi-

tioner. The low offset voltage match and low offset voltage drift

match of the AD708 combine to achieve circuit performance

better than all but the best instrumentation amplifiers. The

outstanding specifications of the AD708, such as open-loop

gain, input offset currents, and low input bias currents, do not

limit circuit accuracy.

In this circuit, the only significant dc errors are due to the offset

voltage of the two amplifiers, the input offset current match of

the amplifiers, and the mismatch of the resistors. Errors

associated with the AD708S contribute less than 0.001% error

over −55°C to +125°C.

As configured, the circuit only requires a gain resistor, R_G, of

suitable accuracy and a stable, accurate voltage reference. The

transfer function is

Maximum error at 25°C

V_O= V_REF[ΔR/(R + ΔR)][R_G/R]

30 μV +

10 kΩ

)

(

1 nA

( )

= 40 μV/10 μV = 4 ppm

10 V

The only significant errors due to the AD708S are

_{OS_OUT}= (V_{OS_MATCH})(2R_G/R) = 30 mV

Maximum error at +125°C or −55°C

50 μV +

2 nA

)

(

10 kΩ

_{OS_OUT}(T) = (V_{OS_DRIFT})(2R_G/R) = 0.3 mV/°C

(

)

= 7 ppm @ +125°C

10 V

To achieve high accuracy, Resistor R_Gshould be 0.1% or better

with a low drift coefficient.

Figure 32 shows V_OUTvs. V_INfor this circuit with a 3 mV input

signal at 0.05 Hz. Note that the circuit exhibits very low offset at

the zero crossing. This circuit can also produce V_OUT= −|V_IN| by

reversing the polarity of the two diodes.

+15V

AD580

2.5V

175kꢀ

R = 350ꢀ

R + ΔR

1/2

AD708

REF

1mV

1/2

AD708

887ꢀ

–15V

Figure 30. Bridge Signal Conditioning Circuit

10kꢀ

IN459

10kꢀ

5kꢀ

= |V |

= 1mV/DIV

IN459

1/2

AD708

10kꢀ

5kꢀ

Figure 32. Absolute Value Circuit Performance

(Input Signal = 0.05 Hz)

3.75kꢀ

1/2

AD708

SELECTION OF PASSIVE COMPONENTS

NOTE

Use high quality passive components to take full advantage of

the high precision and low drift characteristics of the AD708.

Discrete resistors and resistor networks with temperature

coefficients of less than 10 ppm/°C are available from Vishay,

Caddock, Precision Replacement Parts (PRP), and others.

LOW LEAKAGE DIODES

Figure 31. Precision Absolute Value Circuit

PRECISION ABSOLUTE VALUE CIRCUIT

The AD708 is ideally suited to the precision absolute value

circuit shown in Figure 31. The low offset voltage match of the

Rev. C | Page 12 of 16

AD708

OUTLINE DIMENSIONS

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

0.005 (0.13)

MIN

0.055 (1.40)

MAX

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.310 (7.87)

0.220 (5.59)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

PIN 1

0.100 (2.54)

0.100 (2.54) BSC

0.405 (10.29) MAX

BSC

0.060 (1.52)

MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.210

(5.33)

MAX

0.320 (8.13)

0.290 (7.37)

0.015

(0.38)

MIN

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.015 (0.38)

GAUGE

0.060 (1.52)

0.015 (0.38)

0.200 (5.08)

MAX

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

PLANE

SEATING

PLANE

0.150 (3.81)

MIN

0.200 (5.08)

0.125 (3.18)

0.022 (0.56)

0.430 (10.92)

MAX

0.005 (0.13)

MIN

0.018 (0.46)

0.014 (0.36)

0.015 (0.38)

0.008 (0.20)

SEATING

PLANE

0.023 (0.58)

0.014 (0.36)

15°

0°

0.070 (1.78)

0.030 (0.76)

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-001-BA

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP]

Figure 34. 8-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-8)

Narrow Body

(N-8)

Dimensions shown in inches and (millimeters)

ORDERING GUIDE

Model

AD708JN

AD708JNZ¹

AD708AQ

AD708BQ

AD708SQ/883B

Temperature Range

0°C to +70°C

−40°C to +85°C

−55°C to +125°C

Package Description

Package Option

8-Lead Plastic Dual In-Line Package [PDIP]

8-Lead Ceramic Dual In-Line Package [CERDIP]

N-8

Q-8

¹Z = Pb-free part.

Rev. C | Page 13 of 16

AD708

NOTES

Rev. C | Page 14 of 16

AD708

NOTES

Rev. C | Page 15 of 16

AD708

NOTES

registered trademarks are the property of their respective owners.

C05789-0-1/06(C)

Rev. C | Page 16 of 16

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AD708JNZ产品参数

型号:	AD708JNZ
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	DIP
包装说明：	DIP,
针数：	8
Reach Compliance Code：	unknown
风险等级：	5.34
放大器类型：	OPERATIONAL AMPLIFIER
最大平均偏置电流 (IIB)：	0.004 µA
标称共模抑制比：	140 dB
最大输入失调电压：	150 µV
JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e3
长度：	9.88 mm
湿度敏感等级：	NOT APPLICABLE
负供电电压上限：	-22 V
标称负供电电压 (Vsup)：	-15 V
功能数量：	2
端子数量：	8
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT APPLICABLE
认证状态：	COMMERCIAL
座面最大高度：	5.33 mm
标称压摆率：	0.3 V/us
子类别：	Operational Amplifier
供电电压上限：	22 V
标称供电电压 (Vsup)：	15 V
表面贴装：	NO
技术：	BIPOLAR
温度等级：	COMMERCIAL
端子面层：	MATTE TIN
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT APPLICABLE
标称均一增益带宽：	900 kHz
宽度：	7.62 mm
Base Number Matches：	1

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