AD7523, AD7533
Detailed Description
±10V +15V
REF
V
The AD7523 and AD7533 are monolithic multiplying D/A
converters. A highly stable thin film R-2R resistor ladder
network and NMOS SPDT switches form the basis of the
converter circuit, CMOS level shifters permit low power
TTL/CMOS compatible operation. An external voltage or
current reference and an operational amplifier are all that is
required for most voltage output applications.
R2
R
15
14
16
MSB
LSB
FEEDBACK
4
OUT1
OUT2
DATA
INPUTS
AD7523/
AD7533
1
2
-
V
OUT
CR1
6
+
11
GND
3
A simplified equivalent circuit of the DAC is shown in the
Functional Diagram. The NMOS SPDT switches steer the
NOTES:
ladder leg currents between I
and I
buses which
OUT1
OUT2
1. R1 and R2 used only if gain adjustment is required.
must be held at ground potential. This configuration main-
tains a constant current in each ladder leg independent of
the input code.
2. CF1 protects AD7523 and AD7533 against negative transients.
FIGURE 2. UNIPOLAR BINARY OPERATION
Converter errors are further reduced by using separate
metal interconnections between the major bits and the out-
puts. Use of high threshold switches reduce offset (leakage)
errors to a negligible level.
TABLE 1. UNlPOLAR BINARY CODE - AD7523
DIGITAL INPUT
MSB LSB
ANALOG OUTPUT
The level shifter circuits are comprised of three inverters with
positive feedback from the output of the second to the first,
see Figure 1. This configuration results in TTL/CMOS
compatible operation over the full military temperature
range. With the ladder SPDT switches driven by the level
shifter, each switch is binarily weighted for an ON resistance
proportional to the respective ladder leg current. This
assures a constant voltage drop across each switch,
creating equipotential terminations for the 2R ladder
resistors and high accurate leg currents.
255
256
---------
11111111
–V
–V
REF
129
---------
256
10000001
REF
V
128
---------
REF
2
10000000
01111111
00000001
00000000
–V
= –----------------
REF
256
127
---------
–V
–V
REF
REF
256
1
---------
256
V+
1 3
6
4
0
TO LADDER
---------
256
–V
= 0
REF
8
9
NOTE:
–8
1
---------
256
1. 1 LSB = (2 )(V
) =
(V
) .
REF
REF
TTL/
CMOS INPUT
2
5
7
Zero Offset Adjustment
1. Connect all digital inputs to GND.
2. Adjust the offset zero adjust trimpot of the output
I
I
OUT2 OUT1
FIGURE 1. CMOS SWITCH
operational amplifier for 0V ±1mV (Max) at V
.
OUT
Gain Adjustment
Typical Applications
1. Connect all digital inputs to V+.
Unipolar Binary Operation - AD7523 (8-Bit DAC)
1
8
2. Monitor V
OUT
for a -V (1 / ) reading.
REF 2
The circuit configuration for operating the AD7523 in
unipolar mode is shown in Figure 2. With positive and
3. To increase V
, connect a series resistor, R2, (0Ω to
amplifier feedback loop.
OUT
250Ω) in the I
OUT1
negative V
values the circuit is capable of 2-Quadrant
REF
4. To decrease V
OUT
, connect a series resistor, R1, (0Ω to
multiplication. The “Digital Input Code/Analog Output Value”
table for unipolar mode is given in Table 1.
250Ω) between the reference voltage and the V
terminal.
REF
10-11