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产品型号AD7523LN的概述

芯片AD7523LN的概述 AD7523LN是一款具有高精度和低功耗特性的数模转换器(DAC),由美国Analog Devices公司制造。该芯片广泛应用于工业控制、测量仪器和消费电子等领域。AD7523LN的设计基于无失调的电流源和电阻阵列,使其在转换速率和线性度方面表现出色。其主要功能是将数字信号转化为模拟电压或电流输出,支持多种输入格式,适应不同系统的需求。 芯片AD7523LN的详细参数 AD7523LN的主要技术参数包括: - 通道数:包含两个独立的通道(双通道DAC)。 - 分辨率:12位分辨率,具有足够的精度用于大多数专业应用。 - 参考电压范围:可以支持从0V到VDD的参考电压,VDD通常在+4V到+15V之间。 - 增益精度:通常为+1/-1 LSB。 - 转换速率:最高可达10 µs,适合需要快速响应的应用。 - 功耗:在标准工作条件下,静态功耗仅为几毫瓦,非常适合...

产品型号AD7523LN的Datasheet PDF文件预览

AD7523, AD7533  
8-Bit, Multiplying D/A Converters  
August 1997  
Features  
Description  
The AD7523 and AD7533 are monolithic, low cost, high  
performance, 8-bit and 10-bit accurate, multiplying digital-to-  
analog converter (DAC), in a 16 pin DIP.  
• 8-Bit, 9-Bit and 10-Bit Linearity  
• Low Gain and Linearity Temperature Coefficients  
• Full Temperature Range Operation  
• Static Discharge Input Protection  
• TTL/CMOS Compatible  
Intersil’ thin film resistors on CMOS circuitry provide 10-bit  
resolution (8-bit, 9-bit and 10-bit accuracy), with TTL/CMOS  
compatible operation.  
The AD7523 and AD7533s accurate four quadrant  
multiplication, full military temperature range operation, full  
input protection from damage due to static discharge by  
clamps to V+ and GND, and very low power dissipation  
make it a very versatile converter.  
• Supply Range. . . . . . . . . . . . . . . . . . . . . . . .+5V to +15V  
o
• Fast Settling Time at 25 C . . . . . . . . . . . . 150ns (Max)  
• Four Quadrant Multiplication  
Low noise audio gain controls, motor speed controls,  
digitally controlled gain and digital attenuators are a few of  
the wide range of applications of the AD7523 and AD7533.  
• AD7533 Direct AD7520 Equivalent  
Ordering Information  
o
PART NUMBER  
AD7523JN, AD7533JN  
AD7523KN, AD7533KN  
AD7523LN, AD7533LN  
LINEARITY (INL, DNL)  
0.2% (8-Bit)  
TEMP. RANGE ( C)  
PACKAGE  
16 Ld PDIP  
PKG. NO.  
E16.3  
0 to 70  
0.1% (9-Bit)  
0 to 70  
16 Ld PDIP  
16 Ld PDIP  
E16.3  
E16.3  
0.05% (10-Bit)  
0 to 70  
Pinout  
Functional Block Diagram  
AD7523, AD7533  
(PDIP)  
TOP VIEW  
V
10kΩ  
10kΩ  
10kΩ  
10kΩ  
REF IN  
(15)  
20kΩ  
20kΩ  
20kΩ  
20kΩ  
20kΩ  
20kΩ  
I
I
1
2
3
4
5
6
7
8
16 R  
15 V  
OUT1  
FEEDBACK  
OUT2  
GND  
REF IN  
(3)  
14 V+  
NC/BIT 10  
(NOTE 1)  
BIT 1 (MSB)  
BIT 2  
13  
12  
SPDT  
NMOS  
SWITCHES  
I
(2)  
(1)  
OUT2  
NC/BIT 9  
(NOTE 1)  
I
OUT1  
BIT 3  
11 BIT 8  
10 BIT 7  
10kΩ  
BIT 4  
R
MSB  
(4)  
BIT 2  
(5)  
BIT 3  
(6)  
FEEDBACK  
9
BIT 6  
BIT 5  
(16)  
NOTE:  
NOTE: Switches shown for digital inputs “High”  
1. NC for AD7523 only.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
File Number 3105.1  
10-8  
AD7523, AD7533  
Absolute Maximum Ratings  
Thermal Information  
o
Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V Thermal Resistance (Typical, Note 1)  
θJA ( C/W)  
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100  
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V  
REF  
o
Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . .V+ to GND  
Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
Maximum Storage Temperature . . . . . . . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C  
o
o
o
Operating Conditions  
Temperature Range  
JN, KN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to 70 C  
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
Electrical Specifications V+ = +15V, V  
= +10V, V  
OUT1  
= V  
= 0V, Unless Otherwise Specified  
REF  
OUT2  
AD7523  
AD7533  
o
o
T
25 C  
T
MIN-MAX  
T
25 C  
T MIN-MAX  
A
A
A
A
PARAMETER  
SYSTEM PERFORMANCE  
Resolution  
TEST CONDITIONS  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
8
-
-
8
-
-
10  
-
-
10  
-
-
Bits  
Nonlinearity  
J
-10V V  
+10V  
±0.2  
±0.2  
±0.2  
±0.2  
% of  
FSR  
REF  
V
= V  
= 0V  
OUT1  
OUT2  
(Notes 2, 3, 6)  
K, T  
L
-
-
±0.1  
-
-
±0.1  
-
-
±0.1  
-
-
±0.1  
% of  
FSR  
±0.05  
±0.05  
±0.05  
±0.05  
% of  
FSR  
Monotonicity  
Gain Error  
Guaranteed  
Guaranteed  
All Digital Inputs High  
(Note 3)  
-
-
-
-
±1.5  
-
-
-
-
±1.8  
±2  
-
-
-
-
±1.4  
-
-
-
-
±1.8  
±2  
% of  
FSR  
Nonlinearity Tempco  
Gain Error Tempco  
-10V V  
+ 10V  
±2  
±2  
ppm of  
REF  
(Notes 3, 4)  
o
FSR/ C  
±10  
±50  
±10  
±200  
±10  
±50  
±10  
±200  
ppm of  
o
FSR/ C  
Output Leakage Current  
(Either Output)  
V
= V  
OUT2  
= 0  
nA  
OUT1  
DYNAMIC CHARACTERISTICS  
Power Supply Rejection  
V+ = 14.0V to 15.0V  
(Note 3)  
-
±0.02  
-
±0.03  
-
±0.005  
-
±0.008  
% of  
FSR/%  
of V+  
Output Current Settling Time  
Feedthrough Error  
To 0.2% of FSR,  
-
-
150  
-
-
200  
-
-
600  
-
-
800  
ns  
R
= 100(Note 4)  
L
V
= 20V  
P-P  
, 200kHz  
±1/2  
±1  
±0.05  
±0.1  
LSB  
REF  
Sine Wave, All Digital  
Inputs Low (Note 4)  
REFERENCE INPUTS  
Input Resistance (Pin 15)  
All Digital Inputs High  
5
-
-
5
-
-
5
-
-
5
-
-
kΩ  
I
at Ground (Note 4)  
OUT1  
20  
20  
20  
20  
kΩ  
ο
Temperature Coefficient  
-
-500  
-
-500  
-
-300  
-
-300 ppm/ C  
10-9  
AD7523, AD7533  
Electrical Specifications V+ = +15V, V  
= +10V, V  
OUT1  
= V  
= 0V, Unless Otherwise Specified (Continued)  
REF  
OUT2  
AD7523  
AD7533  
o
o
T
25 C  
T
MIN-MAX  
T
25 C  
T MIN-MAX  
A
A
A
A
PARAMETER  
ANALOG OUTPUT  
Output Capacitance  
TEST CONDITIONS  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
C
C
C
C
All Digital Inputs High  
(Note 4)  
-
-
-
-
100  
30  
-
-
-
-
100  
30  
-
-
-
-
100  
35  
-
-
-
-
100  
35  
pF  
pF  
pF  
pF  
OUT1  
OUT2  
OUT1  
OUT2  
All Digital Inputs Low  
(Note 4)  
30  
30  
35  
35  
100  
100  
100  
100  
DIGITAL INPUTS  
Low State Threshold, V  
-
2,4  
-
0.8  
-
-
2,4  
-
0.8  
-
-
2.4  
-
0.8  
-
-
2.4  
-
0.8  
-
V
V
IL  
High State Threshold, V  
IH  
Input Current (Low or High),  
V
= 0V or + 15V  
±1  
±1  
±1  
±1  
µA  
IN  
I , I  
IL IH  
Input Coding  
See Tables 1 and 3  
(Note 4)  
Binary/Offset Binary  
Binary/Offset Binary  
Input Capacitance  
-
-
4
-
4
-
-
4
-
4
pF  
POWER SUPPLY CHARACTERISTICS  
Power Supply Voltage Range  
I+  
(Note 6)  
+5 to +16  
+5 to +16  
V
All Digital Inputs High or  
Low (Excluding Ladder  
Network)  
2
-
2.5  
2
-
2.5  
mA  
NOTES:  
2. Full Scale Range (FSR) is 10V for unipolar and ±10V for bipolar modes.  
3. Using internal feedback resistor, R  
.
FEEDBACK  
4. Guaranteed by design or characterization and not production tested.  
5. Accuracy not guaranteed unless outputs at ground potential.  
6. Accuracy is tested and guaranteed at V+ = +15V, only.  
Definition of Terms  
Nonlinearity: Error contributed by deviation of the DAC Feedthrough Error: Error caused by capacitive coupling  
transfer function from a “best straight line” through the actual from V to I with all digital inputs LOW.  
REF  
OUT1  
plot of transfer function. Normally expressed as  
percentage of full scale range or in (sub)multiples of 1 LSB.  
a
Output Capacitance: Capacitance from I  
terminals to ground.  
, and I  
OUT2  
OUT1  
Resolution: It is addressing the smallest distinct analog  
output change that a D/A converter can produce. It is  
commonly expressed as the number of converter bits. A  
converter with resolution of n bits can resolve output changes  
Output Leakage Current: Current which appears on  
, terminal when all digital inputs are LOW or on I  
I
OUT1  
terminal when all digital inputs are HIGH.  
OUT2  
For further information on the use of this device, see the  
following Application Notes:  
-N  
-N  
of 2 of the full-scale range, e.g., 2  
V
for a unipolar  
REF  
conversion. Resolution by no means implies linearity.  
AnswerFAX  
DOC. #  
Settling Time: Time required for the output of a DAC to  
NOTE #  
DESCRIPTION  
settle to within specified error band around its final value  
1
(e.g., / LSB) for a given digital input change, i.e., all digital  
2
AN002 “Principles of Data Acquisition and  
Conversion”  
9002  
inputs LOW to HIGH and HIGH to LOW.  
Gain Error: The difference between actual and ideal analog  
output values at full-scale range, i.e., all digital inputs at  
HIGH state. It is expressed as a percentage of full scale  
range or in (sub)multiples of 1 LSB.  
AN018 “Do’s and Don’ts of Applying A/D  
Converters”  
9018  
9042  
AN042 “Interpretation of Data Conversion  
Accuracy Specifications”  
10-10  
AD7523, AD7533  
Detailed Description  
±10V +15V  
REF  
V
The AD7523 and AD7533 are monolithic multiplying D/A  
converters. A highly stable thin film R-2R resistor ladder  
network and NMOS SPDT switches form the basis of the  
converter circuit, CMOS level shifters permit low power  
TTL/CMOS compatible operation. An external voltage or  
current reference and an operational amplifier are all that is  
required for most voltage output applications.  
R2  
R
15  
14  
16  
MSB  
LSB  
FEEDBACK  
4
OUT1  
OUT2  
DATA  
INPUTS  
AD7523/  
AD7533  
1
2
-
V
OUT  
CR1  
+
11  
GND  
3
A simplified equivalent circuit of the DAC is shown in the  
Functional Diagram. The NMOS SPDT switches steer the  
NOTES:  
ladder leg currents between I  
and I  
buses which  
OUT1  
OUT2  
1. R1 and R2 used only if gain adjustment is required.  
must be held at ground potential. This configuration main-  
tains a constant current in each ladder leg independent of  
the input code.  
2. CF1 protects AD7523 and AD7533 against negative transients.  
FIGURE 2. UNIPOLAR BINARY OPERATION  
Converter errors are further reduced by using separate  
metal interconnections between the major bits and the out-  
puts. Use of high threshold switches reduce offset (leakage)  
errors to a negligible level.  
TABLE 1. UNlPOLAR BINARY CODE - AD7523  
DIGITAL INPUT  
MSB LSB  
ANALOG OUTPUT  
The level shifter circuits are comprised of three inverters with  
positive feedback from the output of the second to the first,  
see Figure 1. This configuration results in TTL/CMOS  
compatible operation over the full military temperature  
range. With the ladder SPDT switches driven by the level  
shifter, each switch is binarily weighted for an ON resistance  
proportional to the respective ladder leg current. This  
assures a constant voltage drop across each switch,  
creating equipotential terminations for the 2R ladder  
resistors and high accurate leg currents.  
255  
256  
---------  
11111111  
V  
V  
REF  
129  
---------  
256  
10000001  
REF  
V
128  
---------  
REF  
2
10000000  
01111111  
00000001  
00000000  
V  
= –----------------  
REF  
256  
127  
---------  
V  
V  
REF  
REF  
256  
1
---------  
256  
V+  
1 3  
6
4
0
TO LADDER  
---------  
256  
V  
= 0  
REF  
8
9
NOTE:  
8  
1
---------  
256  
1. 1 LSB = (2 )(V  
) =  
(V  
) .  
REF  
REF  
TTL/  
CMOS INPUT  
2
5
7
Zero Offset Adjustment  
1. Connect all digital inputs to GND.  
2. Adjust the offset zero adjust trimpot of the output  
I
I
OUT2 OUT1  
FIGURE 1. CMOS SWITCH  
operational amplifier for 0V ±1mV (Max) at V  
.
OUT  
Gain Adjustment  
Typical Applications  
1. Connect all digital inputs to V+.  
Unipolar Binary Operation - AD7523 (8-Bit DAC)  
1
8
2. Monitor V  
OUT  
for a -V (1 / ) reading.  
REF 2  
The circuit configuration for operating the AD7523 in  
unipolar mode is shown in Figure 2. With positive and  
3. To increase V  
, connect a series resistor, R2, (0to  
amplifier feedback loop.  
OUT  
250) in the I  
OUT1  
negative V  
values the circuit is capable of 2-Quadrant  
REF  
4. To decrease V  
OUT  
, connect a series resistor, R1, (0to  
multiplication. The “Digital Input Code/Analog Output Value”  
table for unipolar mode is given in Table 1.  
250) between the reference voltage and the V  
terminal.  
REF  
10-11  
AD7523, AD7533  
Unipolar Binary Operation - AD7533 (10-Bit DAC)  
3. To increase V  
, connect a series resistor, R2, (0to  
OUT  
250) in the I  
amplifier feedback loop.  
OUT1  
The circuit configuration for operating the AD7533 in  
unipolar mode is shown in Figure 2. With positive and  
4. To decrease V  
OUT  
, connect a series resistor, R1, (0to  
250) between the reference voltage and the V  
terminal.  
negative V  
values the circuit is capable of 2-Quadrant  
REF  
REF  
multiplication. The “Digital Input Code/Analog Output Value”  
table for unipolar mode is given in Table 2.  
Bipolar (Offset Binary) Operation - AD7523  
TABLE 2. UNlPOLAR BINARY CODE - AD7533  
The circuit configuration for operating the AD7523 in the  
bipolar mode is given in Figure 3. Using offset binary digital  
input codes and positive and negative reference voltage  
values, Four-Quadrant multiplication can be realized. The  
“Digital Input Code/Analog Output Value” table for bipolar  
mode is given in Table 3.)  
DIGITAL INPUT  
MSB LSB  
(NOTE 1)  
NOMINAL ANALOG OUTPUT  
1023  
1024  
------------  
1111111111  
1000000001  
V  
V  
REF  
REF  
513  
------------  
1024  
A “Logic 1” input at any digital input forces the corresponding  
ladder switch to steer the bit current to I  
bus. A “Logic  
OUT1  
bus. For any code the  
V
0” input forces the bit current to I  
OUT2  
bus currents are complements of one  
512  
------------  
= –--------------  
REF  
2
1000000000  
0111111111  
0000000001  
0000000000  
V  
I
and I  
REF  
1024  
OUT1  
another. The current amplifier at I  
OUT2  
changes the polarity  
OUT2  
current and the transconductance amplifier at I  
511  
------------  
V  
V  
of I  
REF  
REF  
OUT2  
OUT  
1024  
output sums the two currents. This configuration doubles the  
output range. The difference current resulting at zero offset  
binary code, (MSB = “Logic 1”, all other bits = “Logic 0”), is  
1
------------  
1024  
0
corrected by suing an external resistor, (10M), from V  
------------  
1024  
REF  
V  
= 0  
REF  
to I  
(Figure 3).  
OUT2  
NOTES:  
1. V  
TABLE 3. BlPOLAR (OFFSET BINARY) CODE - AD7523  
as shown in the Functional Diagram.  
OUT  
DIGITAL INPUT  
2. Nominal Full Scale for the circuit of Figure 2 is given by:  
MSB LSB  
ANALOG OUTPUT  
1023  
1024  
------------  
FS = –V  
.
REF  
127  
128  
---------  
11111111  
V  
V  
REF  
3. Nominal LSB magnitude for the circuit of Figure 2 is given by:  
1
1
---------  
128  
10000001  
10000000  
01111111  
00000001  
00000000  
REF  
------------  
LSB = V  
.
REF  
1024  
0
Zero Offset Adjustment  
1
---------  
128  
+V  
+V  
+V  
1. Connect all digital inputs to GND.  
REF  
REF  
REF  
127  
---------  
128  
2. Adjust the offset zero adjust trimpot of the output  
operational amplifier for 0V ±1mV (Max) at V  
.
OUT  
128  
---------  
128  
Gain Adjustment  
1. Connect all digital inputs to V+.  
10  
NOTE:  
7  
1
128  
2. Monitor V  
for a -V  
(1 - 1/2 ) reading.  
OUT  
REF  
---------  
1. 1 LSB = (2 )(V  
) =  
(V  
).  
REF  
REF  
±10V +15V  
REF  
V
R1  
R2  
15  
14  
16  
MSB  
LSB  
R
FEEDBACK  
4
I
OUT1  
DATA  
INPUTS  
AD7523/  
AD7533  
1
2
-
I
R4 5K  
R3 5K  
CR1  
OUT2  
V
OUT  
+
13  
3
R6 10MΩ  
-
CR2  
+
FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)  
10-12  
AD7523, AD7533  
Offset Adjustment  
1. Adjust V to approximately +10V.  
another. The current amplifier at I changes the polarity of  
OUT2  
I
current and the transconductance amplifier at I  
OUT2  
OUT1  
REF  
2. Connect all digital inputs to “Logic 1”.  
3. Adjust I amplifier offset adjust trimpot for 0V±1mV at  
output sums the two currents. This configuration doubles the  
output range. The difference current resulting at zero offset  
binary code, (MSB = “Logic 1”, all other bits = “Logic 0”), is cor-  
OUT2  
amplifier output.  
rected by using an external resistor, (10M), from V  
to  
REF  
I
OUT2  
I
.
OUT2  
4. Connect MSB (Bit 1) to “Logic 1” and all other bits to  
“Logic 0”.  
TABLE 4. UNlPOLAR BINARY CODE - AD7533  
DIGITAL INPUT  
MSB LSB  
(NOTE 1)  
NOMINAL ANALOG OUTPUT  
5. Adjust I  
amplifier offset adjust trimpot for 0V ±1mV  
OUT1  
at V  
.
OUT  
511  
512  
---------  
1111111111  
1000000001  
1000000000  
0111111111  
0000000001  
0000000000  
-V  
-V  
REF  
REF  
Gain Adjustment  
1
1. Connect all digital inputs to V+.  
1
---------  
512  
8
2. Monitor V  
for a -V  
(1 / ) volts reading.  
OUT  
REF 2  
0
3. To increase V  
OUT  
, connect a series resistor, R2, of up to  
and R  
250between V  
.
OUT  
FEEDBACK  
1
---------  
512  
+V  
+V  
+V  
REF  
REF  
REF  
4. To decrease V  
OUT  
, connect a series resistor, R1, of up to  
511  
---------  
512  
250between the reference voltage and the V  
terminal.  
REF  
512  
---------  
512  
Bipolar (Offset Binary) Operation - AD7533  
The circuit configuration for operating the AD7533 in the  
bipolar mode is given in Figure 3. Using offset binary digital  
input codes and positive and negative reference voltage val-  
ues, 4-Quadrant multiplication can be realized. The “Digital  
Input Code/Analog Output Value” table for bipolar mode is  
given in Table 4.  
NOTES:  
1. V  
as shown in the Functional Diagram.  
OUT  
2. Nominal Full Scale for the circuit of Figure 6 is given by:  
1023  
------------  
FSR = V  
.
REF  
512  
3. Nominal LSB magnitude for the circuit of Figure 3 is given by:  
1
A “Logic 1” input at any digital input forces the corresponding  
ladder switch to steer the bit current to I  
bus. A “Logic 0”  
bus. For any code the  
---------  
LSB = V  
.
OUT1  
REF  
512  
input forces the bit current to I  
OUT2  
I
and I  
bus currents are complements of one  
OUT1  
OUT2  
±10V  
BIPOLAR  
ANALOG INPUT  
V+  
V
REF  
15  
14  
16  
MSB  
LSB  
10K  
10K  
R
FEEDBACK  
4
OUT1  
OUT2  
MAGNITUDE  
BITS  
-
1
2
AD7533  
13  
GND  
-
V
5K  
OUT  
DIGITAL  
INPUT  
+
+
3
1
/
IH5140  
2
SIGN BIT  
FIGURE 4. 10-BIT AND SIGN MULTIPLYING DAC  
10-13  
AD7523, AD7533  
Offset Adjustment  
1. Adjust V to approximately +10V.  
Gain Adjustment  
1. Connect all digital inputs to V+.  
REF  
2. Connect all digital inputs to “Logic 1”.  
3. Adjust I amplifier offset adjust trimpot for 0V±1mV at  
-9  
(1 - 2 ) volts reading.  
2. Monitor V  
OUT  
for a -V  
REF  
3. To increase V  
OUT  
, connect a series resistor of up to 250Ω  
OUT2  
amplifier output.  
I
between V  
and R .  
OUT2  
OUT  
FEEDBACK  
4. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”.  
4. To decrease V  
OUT  
, connect a series resistor of up to 250Ω  
between the reference voltage and the V  
terminal.  
REF  
5. Adjust I  
amplifier offset adjust trimpot for 0V ±1mV at  
OUT1  
V
.
OUT  
CALIBRATE  
10K  
4.7K  
6.8V  
(2)  
-
1K  
A2  
SQUARE  
WAVE  
+
+15V  
V
DD NC  
10K 1%  
10K 1%  
15 14 16  
4
MSB  
LSB  
C1  
AD7523/  
AD7533  
OUT1  
OUT2  
DIGITAL FREQUENCY  
CONTROL WORD  
1
-
TRIANGULAR  
WAVE  
A1  
+
13  
2
3
FIGURE 5. PROGRAMMABLE FUNCTION GENERATOR  
V
REF  
+15V  
V
IN  
R
FB  
+15V  
R1  
16  
14  
BIT 1  
-
OUT2  
2
4
MSB  
LSB  
DIGITAL  
INPUT  
“D”  
V
AD7523/  
AD7533  
BIT 1  
OUT  
15 14 16  
4
+
OUT1  
MSB  
1
11  
15  
R2  
DIGITAL  
AD7523/  
AD7533  
BIT 8 (10) (AD7533)  
3
-
1
2
INPUT  
“D”  
V
+
REF  
LSB  
13  
3
BIT 8  
(10) (AD7533)  
-
V
OUT  
+
R
R D  
1
2
V
= V  
---------------------  
---------------------  
OUT  
REF  
R
+ R  
R + R  
1
2
1
2
V
= -V  
IN/D  
OUT  
Where:  
Bit 8  
-----------  
8
Bit 1 Bit 2  
Where D = ----------- + ----------- + …  
Bit 8  
-------------  
2
Bit 1 Bit 2  
D = ------------- + ------------- + …  
1
2
1
2
2
2
2
2
2
2
255  
---------  
256  
255  
---------  
0 D ≤  
0 D ≤  
256  
FIGURE 6. DIVIDER (DIGITALLY CONTROLLED GAIN)  
FIGURE 7. MODIFIED SCALE FACTOR AND OFFSET  
10-14  
AD7523, AD7533  
Die Characteristics  
DIE DIMENSIONS:  
PASSIVATION:  
101 mils x 103 mils (2565micrms x 2616micrms)  
Type: PSG/Nitride  
PSG: 7 ±1.4kÅ  
Nitride: 8 ±1.2kÅ  
METALLIZATION:  
Type: Pure Aluminum  
Thickness: 10 ±1kÅ  
PROCESS:  
CMOS Metal Gate  
Metallization Mask Layout  
AD7523, AD7533  
PIN 4  
BIT 1  
(MSB)  
PIN 7  
BIT 4  
PIN 6  
BIT 3  
PIN 5  
BIT 2  
PIN 3  
GND  
PIN 2  
PIN 8  
BIT 5  
I
2
OUT  
PIN 1  
I
1
OUT  
PIN 9  
BIT 6  
PIN 10  
BIT 7  
PIN 16  
R
FEEDBACK  
PIN 11  
BIT 8  
(LSB)  
PIN 15  
V
REF  
NC  
(PIN 12, BIT 9, AD7533)  
NC  
NC  
NC  
PIN 14  
V+  
(PIN 13, BIT 10, AD7533)  
10-15  
AD7523, AD7533  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate  
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which  
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Mercure Center  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
Intersil (Taiwan) Ltd.  
Taiwan Limited  
7F-6, No. 101 Fu Hsing North Road  
Taipei, Taiwan  
Republic of China  
TEL: (886) 2 2716 9310  
FAX: (886) 2 2715 3029  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (407) 724-7000  
FAX: (407) 724-7240  
10-16  
配单直通车
AD7523LN产品参数
型号:AD7523LN
是否Rohs认证: 不符合
生命周期:Obsolete
IHS 制造商:MAXIM INTEGRATED PRODUCTS INC
零件包装代码:DIP
针数:16
Reach Compliance Code:not_compliant
风险等级:5.91
转换器类型:D/A CONVERTER
输入位码:BINARY, OFFSET BINARY
JESD-30 代码:R-PDIP-T16
JESD-609代码:e0
最大线性误差 (EL):0.05%
位数:8
功能数量:1
端子数量:16
最高工作温度:70 °C
最低工作温度:
封装主体材料:PLASTIC/EPOXY
封装代码:DIP
封装等效代码:DIP16,.3
封装形状:RECTANGULAR
封装形式:IN-LINE
电源:15 V
最大稳定时间:0.2 µs
子类别:Other Converters
最大压摆率:0.1 mA
标称供电电压:15 V
表面贴装:NO
技术:CMOS
温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE
端子节距:2.54 mm
端子位置:DUAL
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