AD8041AR各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号AD8041AR的概述

芯片AD8041AR概述 AD8041AR 是一款高性能、低功耗的运算放大器，属于亚德诺（Analog Devices）公司的产品系列。该芯片具有较高的带宽、极低的失真和卓越的稳定性，是现代电子设计中常见的运算放大器之一。AD8041AR 适合在信号处理、数据采集以及音频设备等领域广泛应用。运算放大器在现代电子设备中起到了基础性的角色，尤其是在模数转换和信号调理的过程中。AD8041AR 的设计目标旨在提供极致的性能，同时满足低功耗的需求，适合电池供电应用。 AD8041AR的详细参数 AD8041AR 的一些关键电气参数包括： 1. 工作电压范围：AD8041AR 支持双极性电源（±5V 至 ±15V）以及单电源供电（3V 至 12V）。 2. 带宽：AD8041AR 的增益带宽积达到 80 MHz，保证了其在高频信号处理中的优异表现。 3. 增益：在直流条件下，AD8041...

产品型号AD8041AR的Datasheet PDF文件预览

160 MHz Rail-to-Rail

Amplifier with Disable

AD8041

CONNECTION DIAGRAM

FEATURES

8-Pin Plastic Mini-DIP and SOIC

Fully Specified for +3 V, +5 V, and ؎5 V Supplies

Output Swings Rail to Rail

Input Voltage Range Extends 200 mV Below Ground

No Phase Reversal with Inputs 1 V Beyond Supplies

Disable/Power-Down Capability

Low Power of 5.2 mA (26 mW on +5 V)

High Speed and Fast Settling on +5 V:

160 MHz –3 dB Bandwidth (G = +1)

160 V/␮s Slew Rate

–INPUT

+INPUT

DISABLE

OUTPUT

AD8041

(Top View)

–V

NC = NO CONNECT

30 ns Settling Time to 0.1%

Good Video Specifications (R_L= 150 ⍀, G = +2)

Gain Flatness of 0.1 dB to 30 MHz

0.03% Differential Gain Error

0.03؇ Differential Phase Error

Low Distortion

–69 dBc Worst Harmonic @ 10 MHz

Outstanding Load Drive Capability

Drives 50 mA 0.5 V from Supply Rails

Cap Load Drive of 45 pF

The output voltage swing extends to within 50 mV of each rail,

providing the maximum output dynamic range. Additionally, it

features gain flatness of 0.1 dB to 30 MHz while offering differ-

ential gain and phase error of 0.03% and 0.03° on a single +5 V

supply. This makes the AD8041 ideal for professional video

electronics such as cameras, video switchers or any high speed

portable equipment. The AD8041’s low distortion and fast set-

tling make it ideal for buffering high speed A-to-D converters.

The AD8041 has a high speed disable feature useful for mul-

tiplexing or for reducing power consumption (1.5 mA). The dis-

able logic interface is compatible with CMOS or open-collector

logic. The AD8041 offers low power supply current of 5.8 mA

max and can run on a single +3 V power supply. These features

are ideally suited for portable and battery powered applications

where size and power are critical.

APPLICATIONS

Power Sensitive High Speed Systems

Video Switchers

Distribution Amplifiers

A/D Driver

Professional Cameras

CCD Imaging Systems

Ultrasound Equipment (Multichannel)

Single-Supply Multiplexer

The wide bandwidth of 160 MHz along with 160 V/µs of slew

rate on a single +5 V supply make the AD8041 useful in many

general purpose high speed applications where dual power sup-

plies of up to ±6 V and single supplies from +3 V to +12 V are

needed. The AD8041 is available in 8-pin plastic DIP and

SOIC over the industrial temperature range of –40°C to +85°C.

PRODUCT DESCRIPTION

The AD8041 is a low power voltage feedback, high speed am-

plifier designed to operate on +3 V, +5 V or ±5 V supplies. It

has true single supply capability with an input voltage range

extending 200 mV below the negative rail and within 1 V of the

positive rail.

= +5V

G = +2

= 400Ω

–1

–2

–3

–4

–5

–6

2.5V

–7

–8

200ns

FREQUENCY – MHz

100

Figure 1. Output Swing: Gain = –1, V_S= +5 V

REV. 0

Figure 2. Frequency Response: Gain = +2, V_S= +5 V

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

AD8041–SPECIFICATIONS^{(@ T}_A^{= +25؇C, V}_S^{= +5 V, R}_L^{= 2 kΩ to 2.5 V, unless otherwise noted)}

AD8041A

Parameter

Conditions

Min

Typ

Max

Units

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, V_O< 0.5 V p-p

Bandwidth for 0.1 dB Flatness

Slew Rate

Full Power Response

Settling Time to 0.1%

G = +1

130

160

MHz

V/µs

MHz

G = +2, R_L= 150 Ω

G = –1, V_O= 2 V Step

V_O= 2 V p-p

G = –1, V_O= 2 V Step

Settling Time to 0.01%

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion

Input Voltage Noise

Input Current Noise

Differential Gain Error (NTSC)

Differential Phase Error (NTSC)

f_C= 5 MHz, V_O= 2 V p-p, G = +2, R_L= 1 kΩ

f = 10 kHz

G = +2, R_L= 150 Ω to 2.5 V

G = +2, R_L= 75 Ω to 2.5 V

–72

nV/√Hz

fA/√Hz

Degrees

600

0.03

0.01

0.19

Degrees

DC PERFORMANCE

Input Offset Voltage

µV/°C

µA

T_MIN–T_MAX

Offset Drift

Input Bias Current

1.2

T_MIN–T_MAX

µA

Input Offset Current

Open-Loop Gain

0.2

0.5

µA

R_L= 1 kΩ

T_MIN–T_MAX

INPUT CHARACTERISTICS

Input Resistance

Input Capacitance

Input Common-Mode Voltage Range

Common-Mode Rejection Ratio

160

1.8

–0.2 to 4

kΩ

V_CM= 0 V to 3.5 V

OUTPUT CHARACTERISTICS

Output Voltage Swing: R_L= 10 kΩ

Output Voltage Swing: R_L= 1 kΩ

Output Voltage Swing: R_L= 50 Ω

Output Current

0.05 to 4.95

0.35 to 4.75 0.1 to 4.9

0.4 to 4.4

0.3 to 4.5

150

V_OUT= 0.5 V to 4.5 V

Sourcing

Sinking

Short Circuit Current

Capacitive Load Drive

G = +1

POWER SUPPLY

Operating Range

Quiescent Current

Quiescent Current (Disabled)

Power Supply Rejection Ratio

5.2

1.4

5.8

1.7

V_S= 0, +5 V, ±1 V

DISABLE CHARACTERISTICS

Turn-Off Time

Turn-On Time

Off Isolation (Pin 8 Tied to –V_S)

Off Voltage (Device Disabled)

On Voltage (Device Enabled)

V_O= 2 V p-p @ 10 MHz, G = + 2

R_F= R_L= 2 kΩ

120

230

<+V_S– 0.25

Open or +V_S

R_L= 100 Ω, f = 5 MHz, G = +2, R_F= 1 kΩ

Specifications subject to change without notice.

–2–

REV. 0

AD8041

(@ T = +25؇C, V = +3 V, R = 2 kΩ to 1.5 V, unless otherwise noted)

SPECIFICATIONS

AD8041A

Typ

Parameter

Conditions

Min

Max

Units

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, V_O< 0.5 V p-p

Bandwidth for 0.1 dB Flatness

Slew Rate

Full Power Response

Settling Time to 0.1%

G = +1

120

150

MHz

V/µs

MHz

G = +2, R_L= 150 Ω

G = –1, V_O= 2 V Step

V_O= 2 V p-p

G = –1, V_O= 2 V Step

Settling Time to 0.01%

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion

Input Voltage Noise

Input Current Noise

Differential Gain Error (NTSC)

Differential Phase Error (NTSC)

f_C= 5 MHz, V_O= 2 V p-p, G = –1, R_L= 100 Ω

f = 10 kHz

G = +2, R_L= 150 Ω to 1.5 V, Input V_CM= 1 V

–55

600

0.07

0.05

nV/√Hz

fA/√Hz

Degrees

DC PERFORMANCE

Input Offset Voltage

µV/°C

µA

T_MIN–T_MAX

Offset Drift

Input Bias Current

1.2

2.3

T_MIN–T_MAX

µA

Input Offset Current

Open-Loop Gain

0.2

0.6

µA

R_L= 1 kΩ

T_MIN–T_MAX

INPUT CHARACTERISTICS

Input Resistance

Input Capacitance

Input Common-Mode Voltage Range

Common-Mode Rejection Ratio

160

1.8

–0.2 to 2

kΩ

V_CM= 0 V to 1.5 V

OUTPUT CHARACTERISTICS

Output Voltage Swing: R_L= 10 kΩ

Output Voltage Swing: R_L= 1 kΩ

Output Voltage Swing: R_L= 50 Ω

Output Current

0.05 to 2.95

0.45 to 2.7 0.1 to 2.9

0.5 to 2.6

0.25 to 2.75

120

V_OUT= 0.5 V to 2.5 V

Sourcing

Sinking

Short Circuit Current

Capacitive Load Drive

G = +1

POWER SUPPLY

Operating Range

Quiescent Current

Quiescent Current (Disabled)

Power Supply Rejection Ratio

5.0

1.3

5.6

1.5

V_S= 0, +3 V, ±0.5 V

DISABLE CHARACTERISTICS

Turn-Off Time

Turn-On Time

Off Isolation (Pin 8 Tied to –V_S)

Off Voltage (Device Disabled)

On Voltage (Device Enabled)

V_O= 2 V p-p @ 10 MHz, G = +2

R_F= R_L= 2 kΩ

170

<+V_S– 0.25

Open or +V_S

R_L= 100 Ω, f = 5 MHz, G = +2, R_F= 1 kΩ

Specifications subject to change without notice.

REV. 0

–3–

AD8041–SPECIFICATIONS^{(@ T}_A^{= +25؇C, V}_S^{= ؎5 V, R}_L^{= 2 kΩ to 0 V, unless otherwise noted)}

AD8041A

Parameter

Conditions

Min

Typ

Max

Units

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, V_O< 0.5 V p-p

Bandwidth for 0.1 dB Flatness

Slew Rate

Full Power Response

Settling Time to 0.1%

G = +1

140

170

MHz

V/µs

MHz

G = +2, R_L= 150 Ω

G = –1, V_O= 2 V Step

V_O= 2 V p-p

G = –1, V_O= 2 V Step

Settling Time to 0.01%

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion

Input Voltage Noise

Input Current Noise

Differential Gain Error (NTSC)

Differential Phase Error (NTSC)

f_C= 5 MHz, V_O= 2 V p-p, G = +2, R_L= 1 kΩ

f = 10 kHz

G = +2, R_L= 150 Ω

G = +2, R_L= 75 Ω

–77

nV/√Hz

fA/√Hz

Degrees

600

0.02

0.03

0.02

0.10

G = +2, R_L= 75 Ω

Degrees

DC PERFORMANCE

Input Offset Voltage

µV/°C

µA

T_MIN–T_MAX

Offset Drift

Input Bias Current

1.2

2.3

T_MIN–T_MAX

µA

Input Offset Current

Open-Loop Gain

0.2

0.6

µA

R_L= 1 kΩ

T_MIN–T_MAX

INPUT CHARACTERISTICS

Input Resistance

Input Capacitance

Input Common-Mode Voltage Range

Common-Mode Rejection Ratio

160

1.8

–5.2 to 4

kΩ

V_CM= –5 V to 3.5 V

OUTPUT CHARACTERISTICS

Output Voltage Swing: R_L= 10 kΩ

Output Voltage Swing: R_L= 1 kΩ

Output Voltage Swing: R_L= 50 Ω

Output Current

–4.95 to +4.95

–4.8 to +4.8

–4.5 to +3.8

100

160

–4.45 to +4.6

–4.3 to +3.2

V_OUT= –4.5 V to 4.5 V

Sourcing

Sinking

Short Circuit Current

Capacitive Load Drive

G = +1

POWER SUPPLY

Operating Range

Quiescent Current

Quiescent Current (Disabled)

Power Supply Rejection Ratio

5.8

1.6

6.5

2.2

V_S= –5, +5 V, ±1 V

DISABLE CHARACTERISTICS

Turn-Off Time

Turn-On Time

Off Isolation (Pin 8 Tied to –V_S)

Off Voltage (Device Disabled)

On Voltage (Device Enabled)

V_O= 2 V p-p @ 10 MHz, G = +2

R_F= 2 kΩ

120

320

<+V_S– 0.25V

Open or +V_S

R_L= 100 Ω, f = 5 MHz, G = +2, R_F= 1 kΩ

Specifications subject to change without notice.

–4–

REV. 0

AD8041

ABSOLUTE MAXIMUM RATINGS¹

MAXIMUM POWER DISSIPATION

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12.6 V

The maximum power that can be safely dissipated by the

AD8041 is limited by the associated rise in junction tempera-

ture. The maximum safe junction temperature for plastic encap-

sulated devices is determined by the glass transition temperature

of the plastic, approximately +150°C. Exceeding this limit tem-

porarily may cause a shift in parametric performance due to a

change in the stresses exerted on the die by the package. Ex-

ceeding a junction temperature of +175°C for an extended pe-

riod can result in device failure.

Internal Power Dissipation²

Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . 1.3 Watts

Small Outline Package (R) . . . . . . . . . . . . . . . . . . 0.9 Watts

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V_S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±3.4 V

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range N, R . . . . . . . . –65°C to +125°C

Operating Temperature Range (A Grade) . . . –40°C to +85°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C

While the AD8041 is internally short circuit protected, this may

not be sufficient to guarantee that the maximum junction tem-

perature (+150°C) is not exceeded under all conditions. To en-

sure proper operation, it is necessary to observe the maximum

power derating curves.

NOTES

¹Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

²Specification is for the device in free air:

2.0

8-PIN MINI-DIP PACKAGE

= +150°C

8-Pin Plastic Package: θ_JA= 90°C/Watt

8-Pin SOIC Package: θ_JA= 160°C/Watt.

1.5

1.0

0.5

ORDERING GUIDE

Temperature

Range

Package

Option

Model

8-PIN SOIC PACKAGE

AD8041AN

AD8041AR

–40°C to +85°C

8-Pin Plastic DIP

8-Pin Plastic SOIC

REEL-SOIC

AD8041AR-REEL

AD8041-EB

Evaluation Board

–50 –40 –30 –20 –10

10 20 30 40 50 60 70 80 90

AMBIENT TEMPERATURE –

°C

Figure 3. Maximum Power Dissipation vs. Temperature

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD8041 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–5–

AD8041–Typical Performance Characteristics

100

= ±2.5V

T = +25°C

91 PARTS

MEAN = +0.21

STD DEVIATION = 1.47

= +5V

T = +25°C

–6 –5 –4 –3 –2 –1

250

500

750

1000 1250

1500

1750

2000

– mV

LOAD RESISTANCE – Ω

Figure 4. Typical Distribution of V_OS

Figure 7. Open-Loop Gain vs. R_Lto +25°C

100

0.20

0.15

0.10

0.05

MEAN = 0.02µV/°C

STD DEV = 2.87µV/°C

SAMPLE SIZE = 45

= +5V

= 1kΩ TO +2.5V

–10

–7.5

–5

–2.5

2.5

7.5

–60 –40 –20

100 120

DRIFT – µV/°C

TEMPERATURE –

Figure 8. Open-Loop Gain vs. Temperature

Figure 5. V_OSDrift Over –40°C to +85°C

100

V = +5V

= 500Ω TO +2.5V

= 50Ω TO +2.5V

= +5V

= 0V

1.5

0.5

1.5

2.5

3.5

4.5

–45 –35 –25 –15 –5

15 25 35 45 55 65 75 85

OUTPUT VOLTAGE – Volts

TEMPERATURE –

Figure 9. Open-Loop Gain vs. Output Voltage

Figure 6. I_Bvs. Temperature

REV. 0

–6–

AD8041

200

150

100

10k

100k

FREQUENCY – Hz

Figure 10. Input Voltage Noise vs. Frequency

Figure 13. Differential Gain and Phase Errors

6.5

6.4

–30

= +3V, A = –1,

= 100Ω TO 1.5V

= +5V

–40

–50

–60

–70

–80

–90

–100

G = +2

6.3

6.2

6.1

6.0

5.9

5.8

5.7

5.6

5.5

= 150Ω TO 2.5V

= 402Ω

= +5V, A = +2,

= 100Ω TO 2.5V

= +5V, A = +1,

= 100Ω TO 2.5V

32.4MHz

= +5V, A = +2,

= 1kΩ TO 2.5V

= +5V, A = +1,

= 1kΩ TO 2.5V

100

500

8 9 10

FREQUENCY – MHz

FUNDAMENTAL FREQUENCY – MHz

Figure 14. 0.1 dB Gain Flatness

Figure 11. Total Harmonic Distortion

–30

–40

+180

+135

+120

+100

+80

10MHz

5MHz

= +5V

= 2kΩ TO +2.5V

= 5pF TO +2.5V

–50

GAIN

–60

–70

+60

–80

1MHz

+40

+20

–90

PHASE

–100

–110

–120

–130

–140

–45

–90

–135

–180

= +5V

= 2kΩ TO +2.5V

GAIN = +2

–20

–40

2.5

OUTPUT VOLTAGE – V

0.5

1.5

3.5

4.5

0.0

0.1

100

500

FREQUENCY – MHz

Figure 12. Worst Harmonic vs. Output Voltage

Figure 15. Open-Loop Gain and Phase Margin

vs. Frequency

REV. 0

–7–

AD8041–Typical Performance Characteristics

V = +5V

G = –1

= 2kΩ TO 2.5V

T = +125°C

C = 5pF

= +3V, 0.1%

G =+1

T = +25°C

= ±5V, 0.1%

T = –55°C

–1

–2

–3

–4

–5

= +3V, 1%

= ±5V, 1%

FREQUENCY – MHz

100

500

0.5

1.5

INPUT STEP – Volts p-p

Figure 16. Closed-Loop Frequency Response

vs. Temperature

Figure 19. Settling Time vs. Input Step

–10

GAIN = +1

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

= +3V

= 2kΩ

V = +3V AND ±5V

& C TO 1.5V

C = 5pF

= +5V

& C TO 2.5V

= ±5V

–1

–2

–3

–4

–5

FREQUENCY – MHz

100

500

0.01

0.1

100

500

FREQUENCY – MHz

Figure 20. CMRR vs. Frequency

Figure 17. Closed-Loop Frequency Response vs. Supply

0.60

0.50

0.40

0.30

0.20

0.10

100

= +5V

GAIN = +1

= +5V

+125

OH,

–55

+5V – V

OH,

+5V – V

, +125

, –55

0.1

0.01

0.1

100

500

FREQUENCY – MHz

LOAD CURRENT – mA

Figure 18. Output Resistance vs. Frequency

Figure 21. Output Saturation Voltage vs. Load Current

REV. 0

–8–

AD8041

100kΩ

= +5V

1kΩ

SERIES

LOAD

= ±5V

= +5V

MARGIN

° PHASE

= +3V

MARGIN

° PHASE

–60 –40 –20

100 120

TEMPERATURE –

°C

SERIES RESISTANCE – Ω

Figure 22. Supply Current vs. Temperature

Figure 25. Capacitive Load vs. Series Resistance

= +5V

= 5KΩ TO +2.5V

= 2kΩ

= +5V

–20

G = +2

–PSRR

–40

–60

+PSRR

–80

–1

–2

–3

–4

–5

G = +5

–100

–120

–140

–160

G = +10

G = +2,

= 402Ω

10M

FREQUENCY – Hz

100M

500M

0.01

0.1

100

500

FREQUENCY – MHz

Figure 26. Frequency Response vs. Closed-Loop Gain

Figure 23. PSRR vs. Frequency

1.600V

= 0.1V p-p

1.575V

1.550V

1.525V

1.500V

1.475V

1.450V

1.425V

1.400V

2kΩ

= +3V

= ±5V

= 2kΩ

G = +1

50mV

10ns

0.1

100

1000

FREQUENCY – MHz

Figure 24. Output Voltage Swing vs. Frequency

Figure 27. Pulse Response, V_S= +3 V

REV. 0

–9–

AD8041–Typical Performance Characteristics

4.840V MAX

= +5V

2.6V

2.55V

2.5V

G = +1

= 2kΩ

= 150Ω TO +2.5V

= 5pF

2.45V

2.4V

0.111V MIN

200µs

50mV

40ns

Figure 28a.

Figure 30. 100 mV Step Response, V_S= +5 V, G = +1

4.741V MAX

= 3V p-p

f = 0.1MHz

2.5V

= 2kΩ

= 150Ω TO GND

= +3V

G = –1

1.5V

0.5V

0.043V MIN

500mV

2µs

200µs

Figure 28b.

Figure 31. Output Swing, V_S= +3 V, V_IN= 3 V p-p

Figure 28a-b. Output Swing vs. Load Reference Voltage,

V_S= +5 V, G = –1

4.5V

= +5V

= 2.8V p-p

f = 0.8MHz

G = +2

2.5V

= 2kΩ

3.5V

2.5V

1.5V

0.5V

= 1V p-p

= +3V

G = –1

1.5V

0.5V

500mV

2µs

40ns

Figure 32. Output Swing, V_S= +3 V, V_IN= 2.8 V p-p

Figure 29. One Volt Step Response, V_S= +5 V, G = +2

REV. 0

–10–

AD8041

Overdrive Recovery

capacitor C9. R1 is the output resistance of the input stage; g_m

is the input transconductance. C7 and C9 provide Miller com-

pensation for the overall op amp. The unity gain frequency will

occur at g_m/C9. Solving the node equations for this circuit

yields:

Overdrive of an amplifier occurs when the output and/or input

range are exceeded. The amplifier must recover from this over-

drive condition. As shown in Figure 33, the AD8041 recovers

within 50 ns from negative overdrive and within 25 ns from

positive overdrive.

V_OUT

g_m2

(sR1[C9 (A2 +1)] + 1) × s

OUTPUT

INPUT

where A0 = g_mg_m2R2 R1 (Open-Loop Gain of Op Amp)

A2 = g_m2R2 (Open-Loop Gain of Output Stage)

2.5V

G = +2

The first pole in the denominator is the dominant pole of the

amplifier, and occurs at about 180 Hz. This equals the input

stage output impedance R1 multiplied by the Miller-multiplied

value of C9. The second pole occurs at the unity-gain band-

width of the output stage, which is 250 MHz. This type of

architecture allows more open-loop gain and output drive to be

obtained than a standard two-stage architecture would allow.

= +5V

50mV

40ns

Figure 33. Overdrive Recovery

Circuit Description

Output Impedance

The AD8041 is fabricated on Analog Devices’ proprietary

eXtra-Fast Complementary Bipolar (XFCB) process which en-

ables the construction of PNP and NPN transistors with similar

f_Ts in the 2 GHz–4 GHz region. The process is dielectrically iso-

lated to eliminate the parasitic and latch-up problems caused by

junction isolation. These features allow the construction of high

frequency, low distortion amplifiers with low supply currents.

This design uses a differential output input stage to maximize

bandwidth and headroom (see Figure 34). The smaller signal

swings required on the first stage outputs (nodes S1P, S1N)

reduce the effect of nonlinear currents due to junction

capacitances and improve the distortion performance. With this

design harmonic distortion of better than –85 dB @ 1 MHz into

100 Ω with V_OUT= 2 V p-p (Gain = +2) on a single 5 volt sup-

ply is achieved.

The low frequency open-loop output impedance of the common

emitter output stage used in this design is approximately 6.5 kΩ.

While this is significantly higher than a typical emitter follower

output stage, when connected with feedback the output imped-

ance is reduced by the open-loop gain of the op amp. With

110 dB of open-loop gain the output impedance is reduced to

less than 0.1 Ω. At higher frequencies the output impedance will

rise as the open-loop gain of the op amp drops; however, the

output also becomes capacitive due to the integrator capacitors

C9 and C3. This prevents the output impedance from ever

becoming excessively high (see Figure 18), which can cause

stability problems when driving capacitive loads. In fact, the

AD8041 has excellent cap-load drive capability for a high-

frequency op amp. Figure 25 demonstrates that the AD8041

exhibits a 45° margin while driving a 20 pF direct capacitive

load. In addition, running the part at higher gains will also

improve the capacitive load drive capability of the op amp.

The complementary common-emitter design of the output stage

provides excellent load drive without the need for emitter fol-

lowers, thereby improving the output range of the device consid-

erably with respect to conventional op amps. High output drive

capability is provided by injecting all output stage predriver cur-

rents directly into the bases of the output devices Q8 and Q36.

Biasing of Q8 and Q36 is accomplished by I8 and I5, along with

a common-mode feedback loop (not shown). This circuit topol-

ogy allows the AD8041 to drive 50 mA of output current with

the outputs within 0.5 V of the supply rails.

I10

Q50

Q39

Q25

R26

R39

Q36

Q51

Q23

Q40

R15 R2

Q22

R27

R23

Q31

Q17

Q13

OUT

Q21

Q27

On the input side, the device can handle voltages from –0.2 V

below the negative rail to within 1.2 V of the positive rail. Ex-

ceeding these values will not cause phase reversal; however, the

input ESD devices will begin to conduct if the input voltages ex-

ceed the rails by greater than 0.5 V.

SIN

SIP

Q11

Q24

Q47

R21

A “Nested Integrator” topology is used in the AD8041 (see

small-signal schematic shown in Figure 35). The output stage

can be modeled as an ideal op amp with a single-pole response

and a unity-gain frequency set by transconductance g_m2and

Figure 34. AD8041 Simplified Schematic

REV. 0

–11–

AD8041

= +5V

100

S1N

OUT

S1P

200ns

Figure 37. 2:1 Multiplexer Performance

Single Supply A/D Conversion

Figure 35. Small Signal Schematic

Disable Operation

Figure 38 shows the AD8041 driving the analog inputs of the

AD9050 in a dc coupled system with single ended signals. All

components are powered from a single +5 V supply. The

AD820 is used to offset the ground referenced input signal to

the level required by the AD9050. The AD8041 is used to add

in the offset with the ground referenced input signal and buffer

the input to AD9050. The nominal input range of the AD9050

The AD8041 has an active-low disable pin, which can be used

to three-state the output of the part and also lower its supply

current. If the disable pin is left floating, the part is enabled and

will perform normally. If the disable pin is pulled to 2.5 V

(min) below the positive supply, output of the AD8041 will be

disabled and the nominal supply current will drop to less than

1.6 mA. For best isolation, the disable pin should be pulled to

as low a voltage as possible; ideally, the negative supply rail.

1000Ω

+5V

The disable pin on the AD8041 allows it to be configured as

an 2:1 mux as shown in Figure 36 and can be used to switch

many types of high speed signals. Higher order multiplexers can

also be built. The break-before-make switching time is approxi-

mately 50 ns to disable the output and 300 ns to enable the

output.

+5V

1000Ω

–0.5V TO +0.5V

AD8041

2.8V – 3.8V

3.3V

AD9050

0.1µF

+5V

1000Ω

0.1µF

10µF

AD820

CH0

5MHz

50Ω

AD8041

G = 2

Figure 38. 10-Bit, 40 MSPS A/D Conversion

is +2.8 V and +3.8 V (1 V p-p centered at +3.3 V). This circuit

provides 40 MSPS analog-to-digital conversion on just 330 mW

of power while delivering 10-bit performance.

330Ω

50Ω

+5V

10µF

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

= 4.9MHz

FUNDAMENTAL = 0.6dB

2nd HARMONIC = 66.9dB

3rd HARMONIC = 74.7dB

SNR = 55.2dB

NOISE FLOOR = – 86.1dB

ENCODE FREQUENCY = 40MHz

CH1

10MHz

50Ω

AD8041

G = 2

330Ω

12 11

74HC04

Figure 36. 2:1 Multiplexer

Figure 39. FFT Output of Circuit in Figure 38

–12–

REV. 0

AD8041

APPLICATIONS

Single Supply Composite Video Line Driver

RGB Buffer

Figure 42 shows a schematic of a single supply gain-of-two com-

posite video line driver. Since the sync tips of a composite video

signal extend below ground, the input must be ac coupled and

shifted positively to provide signal swing during these negative

excursions in a single supply configuration.

The AD8041 can provide buffering of RGB signals that include

ground while operating from a single +3 V or +5 V supply.

The signals that drive an RGB monitor are usually supplied by

current output DACs that operate from a +5 V only supply.

These can triple DACs like the ADV7120 and ADV7122 from

Analog Devices or integrated into the graphics controller IC as

in most PCs these days.

The input is terminated in 75 Ω and ac coupled via C_INto a

voltage divider that provides the dc bias point to the input. Set-

ting the optimal bias point requires some understanding of the

nature of composite video signals and the video performance of

the AD8041.

During the horizontal blanking interval the currents output from

the DACs go to zero and the RGB signals are pulled to ground

via the termination resistors. If more than one RGB monitor is

desired, it cannot simply be connected in parallel because it will

provide an additional termination. Therefore, buffering must be

provided before connecting a second monitor.

Signals of bounded peak-to-peak amplitude that vary in duty

cycle require larger dynamic swing capability than their peak-to-

peak amplitude after ac coupling. As a worst case, the dynamic

signal swing required will approach twice the peak-to-peak

value. The two bounding cases are for a duty cycle that is mostly

low, but occasionally goes high at a fraction of a percent duty

cycle and vice versa.

Since the RGB signals include ground as part of their dynamic

output range, it has previously been required to use a dual sup-

ply op amp to provide this buffering. In some systems this is the

only component that requires a negative supply so it can be

quite inconvenient to incorporate this multiple monitor feature.

Composite video is not quite this demanding. One bounding ex-

treme is for a signal that is mostly black for an entire frame, but

has a white (full intensity), minimum width spike at least once

per frame.

Figure 40 shows a schematic of one channel of a single supply

gain-of-two buffer for driving a second RGB monitor. No cur-

rent is required when the amplifier output is at ground. The ter-

mination resistor at the monitor helps pull the output down at

low voltage levels.

The other extreme is for a video signal that is full white every-

where. The blanking intervals and sync tips of such a signal will

have negative going excursions in compliance with composite

video specifications. The combination of horizontal and vertical

blanking intervals limit such a signal to being at its highest level

(white) for only about 75% of the time.

+3V OR +5V

0.1µF

10µF

As a result of the duty cycle variations between the two extremes

presented above, a 1 V p-p composite video signal that is multi-

plied by a gain of two requires about 3.2 V p-p of dynamic volt-

age swing at the output for an op amp to pass a composite video

signal of arbitrary duty cycle without distortion.

R, G OR B

75Ω

AD8041

75Ω

1kΩ

75Ω

Some circuits use a sync tip clamp along with ac coupling to

hold the sync tips at a relatively constant level in order to lower

the amount of dynamic signal swing required. However, these

circuits can have artifacts like sync tip compression unless they

are driven by sources with very low output impedance.

SECOND RGB

MONITOR

1kΩ

PRIMARY RGB

MONITOR

Figure 40. Single Supply RGB Buffer

Figure 41 is an oscilloscope photo of the circuit in Figure 40

operating from a +3 V supply and driven by the Blue signal of a

color bar pattern. Note that the input and output are at ground

during the horizontal blanking interval. The RGB signals are

specified to output a maximum of 700 mV peak. The output of

the AD8041 is 1.4 V with the termination resistors providing a

divide-by-two. The Red and Green signals can be buffered in

the same manner with duplication of this circuit.

+5V

4.99kΩ

10µF

0.1µF

47µF

COMPOSITE

VIDEO IN

75Ω

COAX

1000µF

OUT

10kΩ

AD8041

75Ω

0.1µF

500mV

5µs

1kΩ

100

220µF

GND

Figure 42. Single Supply Composite Video Line Driver

OUT

The AD8041 not only has ample signal swing capability to

handle the dynamic range required without using a sync tip

clamp, but also has good video specifications like differential

gain and differential phase when buffering these signals in an ac

coupled configuration.

500mV

Figure 41. +3 V, RGB Buffer

REV. 0

–13–

AD8041

To test this, the differential gain and differential phase were

measured for the AD8041 while the supplies were varied. As the

lower supply is raised to approach the video signal, the first ef-

fect to be observed is that the sync tips become compressed be-

fore the differential gain and differential phase are adversely

affected. Thus, there must be adequate swing in the negative di-

rection to pass the sync tips without compression.

Referring to Figure 44, the Green plus sync signal is output

from an ADV7120, a single supply triple video DAC. Because

the DAC is single supply, the lowest level of the sync tip is at

ground or slightly above. The AD8041 is set for a gain of two to

compensate for the divide by two of the output terminations.

500mV

10µs

As the upper supply is lowered to approach the video, the differ-

ential gain and differential phase were not significantly adversely

affected until the difference between the peak video output and

the supply reached 0.6 V. Thus, the highest video level should

be kept at least 0.6 V below the positive supply rail.

100

Taking the above into account, it was found that the optimal

point to bias the noninverting input is at 2.2 V dc. Operating at

this point, the worst case differential gain is measured at 0.06%

and the worst case differential phase is 0.06°.

500mV

The ac coupling capacitors used in the circuit at first glance ap-

pear quite large. A composite video signal has a lower frequency

band edge of 30 Hz. The resistances at the various ac coupling

points—especially at the output—are quite small. In order to

minimize phase shifts and baseline tilt, the large value capacitors

are required. For video system performance that is not to be of

the highest quality, the value of these capacitors can be reduced

by a factor of up to five with only a slightly observable change in

the picture quality.

Figure 44. Single Supply Sync Stripper

The reference voltage for R1 should be twice the dc blanking

level of the G signal. If the blanking level is at ground and the

sync tip is negative as in some dual supply systems, then R1 can

be tied to ground. In either case, the output will have the sync

removed and have the blanking level at ground.

Layout Considerations

The specified high speed performance of the AD8041 requires

careful attention to board layout and component selection.

Proper RF design techniques and low-pass parasitic component

selection are necessary.

Sync Stripper

Some RGB monitor systems use only three cables total and

carry the synchronizing signals along with the Green (G) signal

on the same cable. The sync signals are pulses that go in the

negative direction from the blanking level of the G signal.

The PCB should have a ground plane covering all unused por-

tions of the component side of the board to provide a low im-

pedance path. The ground plane should be removed from the

area near the input pins to reduce the stray capacitance.

In some applications like prior to digitizing component video

signals with A/D converters, it is desirable to remove or strip the

sync portion from the G signal. Figure 43 is a schematic of a cir-

cuit using the AD8041 running on a single +5 V supply that

performs this function.

Chip capacitors should be used for the supply bypassing (see

Figure 45). One end should be connected to the ground plane

and the other within 1/8 inch of each power pin. An additional

large (0.47 µF–10 µF) tantalum electrolytic capacitor should be

connected in parallel, but not necessarily so close, to supply cur-

rent for fast, large signal changes at the output.

GREEN W/SYNC

GREEN W/OUT SYNC

+5V

The feedback resistor should be located close to the inverting

input pin in order to keep the stray capacitance at this node to a

minimum. Capacitance variations of less than 1 pF at the in-

verting input will significantly affect high speed performance.

+0.4

GROUND

10µF

BLANK

0.1µF

GROUND

AD8041

Stripline design techniques should be used for long signal traces

(greater than about 1 inch). These should be designed with a

characteristic impedance of 50 Ω or 75 Ω and be properly termi-

nated at each end.

75Ω

(MONITOR)

1kΩ

0.8V

(2X V

)

BLANK

Figure 43. Single Supply Sync Stripper

–14–

REV. 0

AD8041

Table I. Recommended Component Values

Evaluation Board

An evaluation board for the AD8041 is available which has been

carefully laid out and tested to demonstrate that the specified

high speed performance of the device can be realized. For

ordering information, please refer to the ordering guide.

AD8041A

Gain

Component

+10

R_F

R_G

0 Ω

2 kΩ 400 Ω 2 kΩ 2 kΩ

2 kΩ 400 Ω 500 Ω 220 Ω

The layout of the evaluation board can be used as shown or

serve as a guide for a board layout.

R_O(Nominal)

R_T(Nominal)

Small Signal BW (MHz)

V_S= +5 V

0.1 dB Bandwidth (MHz)

V_S= +5 V

75 Ω 75 Ω 75 Ω 75 Ω 75 Ω

160

Figure 45. Noninverting Configurations for Evaluation

Boards

Figure 47. Board Layout (Component Side)

Figure 48. Board Layout (Back Side)

Figure 46. Evaluation Board Silkscreen (Top)

REV. 0

–15–

AD8041

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Plastic DIP

(N-8)

0.25

(6.35)

0.31

(7.87)

PIN 1

0.30 (7.62)

REF

0.39 (9.91) MAX

0.035±0.01

(0.89±0.25)

0.165±0.01

(4.19±0.25)

0.011±0.003

(0.28±0.08)

0.18±0.03

(4.57±0.76)

0.125

(3.18)

MIN

0°

0.10

(2.54)

0.018±0.003

(0.46±0.08)

0.033

(0.84)

NOM

SEATING

PLANE

BSC

8-Lead Plastic SOIC

(SO-8)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.2440 (6.20)

0.2284 (5.80)

0.1968 (5.00)

0.1890 (4.80)

0.0196 (0.50)

0.0099 (0.25)

x 45°

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0040 (0.10)

0.0500 (1.27)

0.0160 (0.41)

0.0192 (0.49)

0.0138 (0.35)

0.0500

(1.27)

BSC

0.0098 (0.25)

0.0075 (0.19)

–16–

REV. 0

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AD8041AR产品参数

型号:	AD8041AR
Brand Name：	Analog Devices Inc
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	SOIC
包装说明：	PLASTIC, SOIC-8
针数：	8
制造商包装代码：	R-8
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.31.00.01
风险等级：	7.65
放大器类型：	OPERATIONAL AMPLIFIER
架构：	VOLTAGE-FEEDBACK
最大平均偏置电流 (IIB)：	3.5 µA
25C 时的最大偏置电流 (IIB)：	3.2 µA
标称共模抑制比：	80 dB
频率补偿：	YES
最大输入失调电压：	8000 µV
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0
长度：	4.9 mm
低-偏置：	NO
低-失调：	NO
微功率：	NO
湿度敏感等级：	1
负供电电压上限：	-6.3 V
标称负供电电压 (Vsup)：	-5 V
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
包装方法：	TUBE
峰值回流温度（摄氏度）：	240
功率：	NO
电源：	+-1.5/+-6/3/12 V
可编程功率：	NO
认证状态：	Not Qualified
座面最大高度：	1.75 mm
最小摆率：	120 V/us
标称压摆率：	170 V/us
子类别：	Operational Amplifier
最大压摆率：	6.5 mA
供电电压上限：	6.3 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	20
标称均一增益带宽：	170000 kHz
最小电压增益：	17780
宽带：	YES
宽度：	3.9 mm
Base Number Matches：	1

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